Clock Domain Crossing in FPGA

Clock Domain Crossing in FPGA
by Alex Tan on 03-12-2018 at 12:00 pm

Clock Domain Crossing (CDC) is a common occurrence in a multiple clock design. In the FPGA space, the number of interacting asynchronous clock domains has increased dramatically. It is normal to have not hundreds, but over a thousand clock domains interactions. Let’s assess why CDC is a lingering issue, what its impact and the … Read More


Beware of Parameter Variability in Clock Domain Crossings

Beware of Parameter Variability in Clock Domain Crossings
by Jerry Cox on 05-12-2015 at 4:00 pm

How should we assess the risk of harmful metastability in a clock domain crossing (CDC) when the semiconductor process has significant parameter variability? One possibility is to determine the MTBF of a synchronizer at the worst-case corner of the CDC. But that approach has some conflicting complications:

  • Synchronizer failures
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SpyGlass CDC: A Comprehensive solution for addressing CDC issues

SpyGlass CDC: A Comprehensive solution for addressing CDC issues
by Pawan Fangaria on 06-19-2014 at 7:30 am

About a decade ago, semiconductor designs had just a few asynchronous clocks which were easily managed by designers through the process of manual design reviews. The situation today is completely different. An SoC can have hundreds of asynchronous clocks, driving different complex functions, spread across various IPs, supplied… Read More