S2C’s Virtex UltraScale Prototyping Provides Designers Much Needed Flexibility

S2C’s Virtex UltraScale Prototyping Provides Designers Much Needed Flexibility
by Majeed Ahmad on 05-18-2015 at 12:00 pm

The advent of large system-on-chip (SoC) designs has brought FPGA prototyping hardware into the limelight and the launch of S2C Inc.’s Single VU440 Prodigy Logic Module just shows how far off-the-shelf prototyping has come in a bid to complement hardware verification and software development. Hardware verification… Read More


Breaking the SoC lab walls

Breaking the SoC lab walls
by Don Dingee on 05-11-2015 at 7:00 am

There used to be this thing called the “computer lab”, with glowing rows of terminals connected to a mainframe or minicomputer. Computers required a lot of care and feeding, with massive cooling and power requirements. Microprocessors and personal computers appeared in the 1970s, with much smaller and less expensive machines… Read More


Automating Timing Closure Using Interconnect IP, Physical Information

Automating Timing Closure Using Interconnect IP, Physical Information
by Majeed Ahmad on 04-29-2015 at 1:00 pm

Timing closure is a “tortoise” for some system-on-chip (SoC) designers just the way many digital guys call RF design a “black art”. Chip designers often tell horror stories of doing up to 20 back-end physical synthesis place & route (SP&R) iterations with each iteration taking a week or more. “Timing closure”, a largely… Read More


Managing Design Flows in RF Modules

Managing Design Flows in RF Modules
by Majeed Ahmad on 04-24-2015 at 7:00 pm

The semiconductor industry is expected to grow at a reasonable pace in 2015 and beyond, with the biggest market being compute applications followed by wireless and consumer applications. The highest growth, however, is expected to be in application-specific products for devices such as smartphones, wearables, memories, … Read More


Rockchip Bets on Arteris FlexNoC Interconnect IP to Leapfrog SoC Design

Rockchip Bets on Arteris FlexNoC Interconnect IP to Leapfrog SoC Design
by Majeed Ahmad on 04-19-2015 at 9:00 am

China was a virgin territory for Arteris Inc. before July 19, 2012 when Fuzhou Rockchip Electronics announced that it has licensed the Arteris FlexNoC network-on-chip (NoC)-based interconnect IP technology for its multicore SoCs for budget Android tablets. Rockchip mostly targets the tablet and set-top box (STB) markets … Read More


Chips and pins and layers within

Chips and pins and layers within
by Don Dingee on 03-25-2015 at 3:00 pm

After teams sweat the details of SoC and industrial design, they turn to printed circuit board designers for magic. Here are a pile of chips and passives, and a schematic for interconnecting them. This is how much physical space the board can occupy. Connectors have to be here, and here, and mounting holes there, and there. There … Read More


Xilinx ships the VU440 and its 4M logic cells

Xilinx ships the VU440 and its 4M logic cells
by Don Dingee on 01-27-2015 at 8:00 pm

Xilinx has delivered not only “the biggest FPGA on the planet”, but what it claims is currently the world’s largest integrated circuit: the Virtex UltraScale VU440, with 19 billion transistors fabbed in TSMC 20nm. The list of first customers to receive parts says a lot about the state of SoC design today, and the vital role FPGA-based… Read More


SoCs should invest in a strong cache position

SoCs should invest in a strong cache position
by Don Dingee on 12-30-2014 at 4:00 pm

Like most technology firms, Apple has been home to many successes, and some spectacular defeats. One failure was Project Aquarius. At the dawn of the RISC era, before ARM architecture was “discovered” in Cupertino, engineers were hunkered over a Cray X-MP/48. The objective was to design Apple’s own quad core RISC processor to … Read More


3 reasons to focus on hardware dependent software

3 reasons to focus on hardware dependent software
by Don Dingee on 10-25-2014 at 4:00 pm

Why is software for modern SoCs so blasted expensive to develop? One reason is more software is being developed at the kernel layer – hardware dependent software, or HdS. Application software often assumes the underlying hardware, operating system, communication stacks, and device drivers are stable. For HdS, this flawed assumption… Read More


CEVA creating a wearable IP platform

CEVA creating a wearable IP platform
by Don Dingee on 07-25-2014 at 12:00 am

Processor and GPU cores usually get the limelight, driven by the ARM and Imagination machines occupying the center square of most SoC designs. CEVA has quietly been assembling DSP IP in most of the squares around the edge, and may have just reached critical mass for wearables and IoT devices.… Read More