Second FPGA to the right, and straight on ‘til it works

Second FPGA to the right, and straight on ‘til it works
by Don Dingee on 11-26-2012 at 6:00 pm

In a fantasy world where there were no coding errors or integration issues, FPGA designs would fly straight through synthesis easily and quickly. Maybe that world does exist somewhere. For the rest of us, who have experienced the agony of running a large FPGA design – again – only to find another error and have to start over, there … Read More


The logic of trusting FPGAs through DO-254

The logic of trusting FPGAs through DO-254
by Don Dingee on 11-13-2012 at 8:15 pm

Any doubters of the importance of FPGA technology to the defense/aerospace industry should consider this: each Airbus A380 has over 1000 Microsemi FPGAs on board. That is a staggering figure, especially considering the FAA doesn’t trust FPGAs, or the code that goes into them.… Read More


Next Generation FPGA Prototyping

Next Generation FPGA Prototyping
by Paul McLellan on 11-12-2012 at 7:00 am

One technology that has quietly gone mainstream in semiconductor design is FPGA prototyping. That is, using an FPGA version of the design to run extensive verification. There are two approaches to doing this. The first way is simply to build an prototype board, buy some FPGAs from Xilinx or Altera and do everything yourself. The… Read More


A Brief History of Aldec

A Brief History of Aldec
by Daniel Payne on 10-20-2012 at 5:31 pm

Dr. Stanley Hyduke founded Aldecin 1984 and their first product was delivered in 1985, named SUSIE (Standard Universal Simulator for Improved Engineering), a gate-level, DOS-based simulator. The SUSIE simulator was priced lower than other EDA vendor tools from the big three: Daisy, Mentor and Valid (aka DMV). Aldec maintains… Read More


Xilinx Programmable Packet Processor

Xilinx Programmable Packet Processor
by Paul McLellan on 10-17-2012 at 5:19 pm

At the Linley conference last week I ran into Gordon Brebner of Xilinx. He and I go a long way back. We had adjacent offices in Edinburgh University Computer Science Department back when we were doing our PhDs and conspiring to network the department’s Vax into the university network over a two-week vacation. We managed to … Read More


12m FPGA prototyping sans partitioning

12m FPGA prototyping sans partitioning
by Don Dingee on 10-16-2012 at 9:30 pm

FPGA-based prototyping brings SoC designers the possibility of a high-fidelity model running at near real-world speeds – at least until the RTL design gets too big, when partitioning creeps into the process and starts affecting the hoped-for results.

The average ASIC or ASSP today is on the order of 8 to 10M gates, and that includes… Read More


Altera’s Real Impact with ARM based SOC FPGAs

Altera’s Real Impact with ARM based SOC FPGAs
by Ed McKernan on 10-16-2012 at 8:15 pm

At the annual Linley Processor Conference this past week a number of chip vendors proposed a raft of new networking solutions directed at solving today’s bandwidth issues. Perhaps the overall highlight of the conference was the recognition by Keynote Speaker Linley Gwennap of the shift that is taking place towards ARM based solutions.… Read More


Altera’s Use of Virtual Platforms

Altera’s Use of Virtual Platforms
by Paul McLellan on 10-11-2012 at 9:00 pm

Altera have been making use of Synopsys’s virtual platform technology to accelerate the time to volume by letting software development proceed in parallel with semiconductor development so that the software development does not need to wait until availability of hardware.

In the past, creating the virtual platform … Read More


The Middle is A Bad Place to Be if You’re a CPU Board

The Middle is A Bad Place to Be if You’re a CPU Board
by Don Dingee on 10-09-2012 at 10:45 pm

In a discussion with one of my PR network recently, I found myself thinking out loud that if the merchant SoC market is getting squeezed hard, that validates something I’ve been thinking – the merchant CPU board market is dying from the middle out.… Read More


Aldec-Altera DO-254

Aldec-Altera DO-254
by Daniel Nenni on 09-25-2012 at 9:58 pm

As described in DO-254, any inability to verify specific requirements by test on the device itself must be justified, and alternative means must be provided. Certification authorities favor verification by test for formal verification credits because of the simple fact that hardware flies not simulation models. RequirementsRead More