VLSIT Conference – imec on CFETs

VLSIT Conference – imec on CFETs
by Scotten Jones on 07-16-2018 at 12:00 pm

The 2018 VLSI Technology conference was held in Hawaii in June and is one of the premier conferences covering integrated circuit process technology and circuit design. The Complementary FET (CFET) is an emerging option to continue logic scaling into the next decade. At the conference imec, GLOBALFOUNDRIES, Tokyo Electron and… Read More


Mentor Calibre Panel

Mentor Calibre Panel
by Alex Tan on 07-09-2018 at 12:00 pm

Getting your tape-out done on time is hard, but can it be made easier? That was the main topic of Mentor’s Calibre Panel held at DAC 2018, attended by a few key players in IC design ecosystem: Bob Stear, VP of Marketing at Samsung represented the foundry side; from the IP side, Prasad Subramaniam, VP of eSilicon for R&D and Technology;… Read More


Imec technology forum 2018 – the future of scaling

Imec technology forum 2018 – the future of scaling
by Scotten Jones on 06-27-2018 at 12:00 pm

At the Imec technology forum in Belgium, Dan Mocuta and Juliana Radu presented “Evolution and Disruption: A Perspective on Logic Scaling and Beyond”, I also had a chance to sit down with Dan and discuss the presentation.

Device scaling

Scaling of devices will only get you so far, you need to look at new devices and new… Read More


Imec Technology Forum: Gary Patton of GLOBALFOUNDRIES

Imec Technology Forum: Gary Patton of GLOBALFOUNDRIES
by Scotten Jones on 05-31-2018 at 12:00 pm

The imec technology forum was held in Belgium last week. At the forum I had a chance to sit down with Gary Patton the CTO of GLOBALFOUNDRIES (GF) for an interview and he also presented “Enabling Connected Intelligence – Technology innovation: Enablers for an intelligent future” at the forum. In this article … Read More


SPICE Model Generation by Machine Learning

SPICE Model Generation by Machine Learning
by Thomas Blaesi on 05-18-2018 at 12:00 pm

It was 1988 when I got into SPICE (Simulation Program with Integrated Circuit Emphasis)while I was characterizing a 1.5 μm Standard cell library developed by students at my Alma-Mata Furtwangen University in Germany. My professor Dr. Nielinger was not only my advisor he also wrote the first SPICE bible in German language.… Read More


Retooling Implementation for Hot Applications

Retooling Implementation for Hot Applications
by Bernard Murphy on 05-17-2018 at 7:00 am

It might seem I am straying from my normal beat in talking about implementation; after all, I normally write on systems, applications and front-end design. But while I’m not an expert in implementation, I was curious to understand how the trending applications of today (automotive, AI, 5G, IoT, etc.) create new demands on implementation,… Read More


TSMC Technologies for IoT and Automotive

TSMC Technologies for IoT and Automotive
by Alex Tan on 05-15-2018 at 12:00 pm

At TSMC 2018 Silcon Valley Technology Symposium, Dr Kevin Zhang, TSMC VP of Business Development covered technology updates for IoT platform. The three growth drivers in this segment namely TSMC low power, RF enhancement and embedded memory technology (MRAM/RRAM) reinforced both progress and growth in global semiconductorRead More


TSMC Technologies for Mobile and HPC

TSMC Technologies for Mobile and HPC
by Alex Tan on 05-10-2018 at 12:00 pm

During TSMC 2018 Technology Symposium, Dr. B.J. Woo, TSMC VP of Business Development presented market trends in the area of mobile applications and HPC computing as well as shared TSMC progress in making breakthrough efforts in the technology offerings to serve these two market segments.

Both 5G and AI are taking the center stage… Read More


imec and Cadence on 3nm

imec and Cadence on 3nm
by Daniel Nenni on 04-30-2018 at 7:00 am

One of the more frequent questions I get, “What is next after FinFETs?” is finally getting answered. Thankfully I am surrounded by experts in the process technology field including Scotten Jones of IC Knowledge. I am also surrounded by design enablement experts so I really am the man in the middle which brings us to a discussion between… Read More


Monitoring Process, Voltage and Temperature in SoCs, webinar recap

Monitoring Process, Voltage and Temperature in SoCs, webinar recap
by Daniel Payne on 04-26-2018 at 4:00 pm

Have you ever wondered how process variation, thermal self-heating and Vdd levels affect the timing and yield of your SoC design? If you’re clock specification calls for 3GHz, while your silicon is only yielding at 2.4GHz, then you have a big problem on your hands. Such are the concerns of many modern day chip designers. To… Read More