Webinar: Fast and Accurate High-Sigma Analysis with Worst-Case Points

Webinar: Fast and Accurate High-Sigma Analysis with Worst-Case Points
by Daniel Payne on 11-02-2023 at 10:00 am

Worst case point min

IC designers are tasked with meeting specifications like robustness in SRAM bit cells where the probability of a violation are lower than 1 part-per-billion (1 ppb). Another example of robustness is a Flip-Flop register that must have a probability of specification violation lower than 1 part-per-million (1 ppm). Using Monte… Read More


Keynote Speakers Announced for IDEAS 2023 Digital Forum

Keynote Speakers Announced for IDEAS 2023 Digital Forum
by Daniel Nenni on 10-26-2023 at 10:00 am

ideas 400X400

As we all know, hearing directly from the people who actually use EDA tools, people who are solving real world problems with the latest technologies are the best source of information. Thus EDA User group meetings are always first on my event list every year which brings us to Ansys Ideas.

Ansys User Group Meeting Features Technical

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Why Secure Ethernet Connections?

Why Secure Ethernet Connections?
by Daniel Payne on 05-29-2023 at 6:00 am

Ethernet Security min

While web browsing I constantly glance for the padlock symbol to indicate that the site is encrypting any of my form data by using the https prefix, which means that an SSL (Secure Sockets Layer) certificate is being used by the web hosting company. I have peace of mind knowing that my credit card information cannot be easily stolen… Read More


Takeaways from CadenceLIVE 2023

Takeaways from CadenceLIVE 2023
by Bernard Murphy on 05-11-2023 at 6:00 am

Takeways image

Given popular fascination it seems impossible these days to talk about anything other than AI. At CadenceLIVE, it was refreshing to be reminded that the foundational methods on which designs of any type remain and will always be dominated in all aspects of engineering by deep, precise, and scalable math, physics, computer science… Read More


Podcast EP156: A Chat With Shankar Krishnamoorthy About Strategy and Outlook for EDA Development at SNUG

Podcast EP156: A Chat With Shankar Krishnamoorthy About Strategy and Outlook for EDA Development at SNUG
by Daniel Nenni on 04-21-2023 at 10:00 am

This is another special edition of our podcast series. SemiWiki staff writer Kalar Rajendiran spoke with Shankar Krishnamoorthy, General Manager, Electronic Design Automation Group for Synopsys at the recent SNUG meeting,

Shankar discusses how Synopsys is focusing on hyperconvergence and implementation of AI across the… Read More


Cadence Hosts ESD Alliance Seminar on New Export Regulations Affecting EDA and SIP March 28

Cadence Hosts ESD Alliance Seminar on New Export Regulations Affecting EDA and SIP March 28
by Bob Smith on 03-10-2023 at 6:00 am

ESD Alliance Export Seminar 2023

Anyone interested in learning about general trade compliance concepts or how export control and sanction regulations affect the electronic systems design ecosystem will want to attend the upcoming ESD Alliance export seminar. It will be hosted by Ada Loo, chair of the ESD Alliance Export Committee and Cadence’s Group Director… Read More


Building better design flows with tool Open APIs – Calibre RealTime integration shows the way forward

Building better design flows with tool Open APIs – Calibre RealTime integration shows the way forward
by Peter Bennet on 12-22-2022 at 10:00 am

calibre real time digital and custom

You don’t often hear about the inner workings of EDA tools and flows – the marketing guys much prefer telling us about all the exciting things their tools can do rather than the internal plumbing. But this matters for making design flows – and building these has largely been left to the users to sort out. That’s an increasing challenge… Read More


Podcast EP132: The Growing Footprint of Methodics IPLM with Simon Butler

Podcast EP132: The Growing Footprint of Methodics IPLM with Simon Butler
by Daniel Nenni on 12-16-2022 at 10:00 am

Dan is joined by Simon Butler, the founder and CEO of Methodics Inc, Methodics was acquired by Perforce in 2020, and he is currently the general manager of the Methodics business unit at Perforce. Methodics created IPLM as a new business segment in the enterprise software space to service the needs of IP and component based design.… Read More


Cracking post-route Compliance Checking for High-Speed Serial Links with HyperLynx

Cracking post-route Compliance Checking for High-Speed Serial Links with HyperLynx
by Peter Bennet on 12-15-2022 at 6:00 am

hyperlynx flow

SemiWiki readers from a digital IC background might find it surprising that post-PCB route analysis for high speed serial links isn’t a routine and fully automated part of the board design process. For us, the difference between pre- and post-route verification is running a slightly more accurate extraction and adding SI modelling,… Read More


The Role of Clock Gating

The Role of Clock Gating
by Steve Hoover on 11-28-2022 at 10:00 am

The Role of Clock Gating

Perhaps you’ve heard the term “clock gating” and you’re wondering how it works, or maybe you know what clock gating is and you’re wondering how to best implement it. Either way, this post is for you.

Why Power Matters

I can’t help but laugh when I watch a movie where the main characters are shrunk… Read More