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TechInsights
Posted on by Scotten Jones

Setting the Record Straight on FD-SOI Costs

Setting the Record Straight on FD-SOI Costs
by Scotten Jones on 07-20-2014 at 7:00 pm
Categories: Semiconductor Services, TechInsights

I recently published an article on Semiwiki “Is SOI Really Less Expensive”. That article was the result of months of careful research and analysis. I looked at planar FDSOI versus bulk planar, bulk FinFETs and FinFETs on SOI at three different nodes. I took a consistent set of assumptions with respect to the fab used to run the processes, the number of metal layers, Vts, etc. to develop the fairest direct comparison I could construct. During this process I consulted with wafer manufacturers, technical experts, technical papers, patents and other sources. I then ran all of the different processes through the commercial IC Knowledge – Strategic Cost Model tool.

My original article with comments is posted here: https://www.legacy.semiwiki.com/forum/content/3599-soi-really-less-expensive.html

Soon after I published the aforementioned article, Eric Esteve published a lengthy comment on the article. His comment is available on Semiwiki appended to my original article for anyone interested in reading it, but there are a couple of key points that I would like to address here. In his comment Mr. Esteve made two key claims relative to my cost analysis and conclusions. The first was that I overestimated the cost of the SOI wafers in full production. The second was that I compared a FinFET with 3 Vts to planar FDSOI and that I should be using 4Vts or even 5Vts for the bulk FinFET. Mr. Esteve then goes on to conclude that the starting FDOSI wafer price should be reduced giving a 5% reduction in cost relative to FinFETs on bulk and that changing the FinFET on bulk to 4Vts would also give a 5% reduction. In total he then claims that the relative cost for FDSOI versus FinFETs on bulk should be 10% better than my calculation. As a side note here my calculation was that FinFETs on bulk are 6% less expensive to produce than planar FDSOI so if Mr. Esteve’ analysis were correct FDSOI would now be 4% less expensive.

In the comment section for my original article I replied to Mr. Esteve’ comment explaining that 3Vts are sufficient for many designs and that running the numbers, starting FDSOI wafer costs would have to be cut in half just to reach cost parity with bulk FinFETs. ,

After Mr. Esteve posted his comment, but apparently before I posted my reply, Adele Hars, editor in chief of Advanced Substrate News took Mr. Esteve’s comments and made them into an article on Advanced Substrate News entitled “Is FD-SOI Cheaper? Why Yes!” For those of you who don’t know, Advanced Substrate News is a publication that promotes SOI. I first became of aware of this from LinkedIn where Ms. Hars posted a link to the article. I commented on Ms. Hars’ LinkedIn post that Mr Esteve’ analysis was incorrect, I even went back and found that adding a 4[SUP]th[/SUP] Vt to the FinFET on bulk only changed the result by 1% and that the FDSOI starting wafer cost would still have to be cut in half to reach cost parity with FinFETs on bulk. Ironically Ms. Hars’ commented in her article that the “devil is in the details” while quoting Mr Esteve’ analysis that gets the details of his calculation wrong! I found that I can now only find Ms. Hars’ post and discussion on LinkedIn in the FD-SOI design community and my comments are missing. I have also tried twice to comment on the article directly on the Advanced Substrate News web site and both times my comments have failed to appear.

[UPDATE – after I posted this article Adele Hars contacted me and reported she had been unable to access the Advanced Substrate News web site for several days and has now posted my comment. I want to publicly acknowledge here that I very much appreciate this support of open debate.]

The LinkedIn post is here: https://www.linkedin.com/groups/Debate-raging-on-costs-FinFET-5155646.S.5890494542842470403

The Advanced Substrate News article is here: http://www.advancedsubstratenews.com/2014/06/is-fd-soi-cheaper-why-yes/

Mr Esteve has now taken his comments and expended on them in a new Semiwiki article. The article is available for the interested reader on the Semiwiki web site but he basically repeats the criticism from his comment on my article while adding in that my article is “slightly biased”. In the comments he also says my results are “10% biased”.

Mr Esteve’ new article is here: https://www.legacy.semiwiki.com/forum/content/3674-keywords-fd-soi-cost-finfet.html?postid=14967#comments_14967

In the interest of “setting the record straight” I would like to make a few comments on all of this:

[LIST=1]

  • In my original work I found a 6% cost advantage for FinFETs on bulk versus FDSOI at 14nm. This was based on 3Vts, Mr. Esteve believes this is unfair and that I should be using 4Vts or 5Vts. If you read all the comments on both my article and Mr. Esteve’ recent article you will see that there are comments both agreeing and disagreeing with Mr. Esteve. It appears that this is a point where knowledgeable experts disagree and is likely application specific.
  • In the interest of addressing Mr. Esteve’ concerns I have rerun my analysis with 4Vts for FinFET on bulk and found that FinFET on bulk is still 5% less expensive than FDSOI. Mr. Esteve’ 5% change for adding a Vt is incorrect, the correct value is 1% for FinFET on bulk.
  • The starting wafer prices I used in my analysis came from discussions with manufacturers of both SOI and Epi wafers and reflect current pricing for both. I agree that FDSOI prices will likely come down if and when FDSOI volumes ramp up, but they will have to come down 40% or even 50% for FDSOI to reach parity with FinFET on bulk costs. With 14nm ramping later this year that seems like an awfully big drop to me.
  • The FD-SOI design community on LinkedIn and Advanced Substrate News both appear to be blocking or deleting my comments. In my opinion that kind of censorship has no place in this kind of debate. I would like to contrast this to Semiwiki owned by Daniel Nenni. Mr. Nenni publishes a lot of articles on Semiwiki that are hotly debated and I have seen many comments strongly disagreeing with Mr. Nenni views published on Semiwiki. Whether you agree with Mr. Nenni’ viewpoints or not, I believe his lack of censorship is to be applauded. It also in my opinion makes Semiwiki a more credible site for technical information and debate.
  • ​Mr. Esteve uses the phrases “slightly biased” and “10% biased” in his article and comments when referring to my work. If you google “bias” the first definition that comes up is “prejudice in favor of or against one thing, person, or group compared with another, usually in a way considered to be unfair.” I can’t speak to whether that is what Mr Esteve’ actually meant when he used the word “biased” but that is the common usage of the word. I have no allegiance to either FDSOI or FinFETs. I have clients deeply involved in both technologies. Ironically I have actually led process development efforts on SOI, I am coauthor of two issued patents on high voltage integrated circuit technology on SOI, and by the late nineties the operation I led had sold over 10 million ICs on SOI!

    In closing I would just like to point out that after all this analysis and debate the conclusion from my original article still stands:

    “Using the same yield per mask layer assumptions for both planar FDSOI and FinFETs it has been shown that the costs for planar FDSOI and FinFETs on bulk or SOI are all comparable at the 14nm node. Decisions on which process to pursue are therefore expected to be driven by factors other than cost.”

    Scotten W. Jones, President, IC Knowledge LLC

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