Webinar: Challenges in creating large High Performance Compute SoCs in advanced geometries

When we think about Compute and AI SoCs, we often focus on the huge numbers of calculations being carried out every second, and the ingenious IPs that are able to reach such high levels of performance. However, there also exists a significant challenge in keeping the vast quantities of data flowing around the chip which is solved by using a Network on Chip (NoC). In this webinar, we be discussing some of the challenges involved in developing such NoCs, and what we can do to overcome them.

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NoCs are very complex IPs which touch almost every part of an SoC. They are intrinsically linked to the chip’s floorplan, architecture, functional requirements, startup, security, safety and many other aspects. The functional correctness and performance capabilities of a NoC can also be time consuming and difficult to verify. High performance NoCs can also take up significant area on a chip.

All of this means that there can be a high likelihood that the NoC will suffer change through the life of the project, and this change can ultimately disrupt the floorplan, and therefore have a significant impact on the whole chip.

To try and reduce the probability of this disruption happening, we use various tools to allow us to carry out performance exploration and verification early in the process. By securing the requirements early on, and being able to quickly verify NoC spins meet those requirements, we can also stabilize the floorplan, and reduce unnecessary churn in the design.

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Webinar abstract: The challenges in creating AI and High Performance Compute chipsets are not only limited to those around developing IPs that can carry out large numbers of calculations per second. To allow these number-crunching IPs to do their calculations also requires increasingly large volumes of data to be moved around the SoC at high speed. Sondrel explains how this can be done with a customized Network on Chip (NoC) solution.

What you’ll learn: The challenges and solutions for developing a Network on Chip as part of a large complex SoC. Who should attend: People working on or commissioning large SoCs

Presenter: Ben Fletcher is Director of Engineering at Sondrel and is involved in all aspects of SoC development from initial customer engagement through to bring-up and validation. He has over 20 years of experience primarily in ASIC and SoC development within the consumer electronics market, specializing in architecture of Audio, Video and AI chipsets.

About Sondrel™
Founded in 2002, Sondrel is the trusted partner of choice for handling every stage of an IC’s creation. Its award-winning, define and design ASIC consulting capability is fully complemented by its turnkey services to transform designs into tested, volume-packaged silicon chips. This single point of contact for the entire supply chain process ensures low risk and faster times to market. Headquartered in the UK, Sondrel supports customers around the world via its offices in China, India, France, Morocco and North America. For more information, visit www.sondrel.com

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