In the first four installments of this series we have examined Moore’s law, described the drivers that have enabled Moore’s law and discussed the specific status and issues around DRAM and logic. In this final installment we will examine NAND Flash.
2D NAND flash technology challenges
Similar to DRAM discussed in the third installment in this series, NAND flash has peripheral CMOS and a memory array. Once again the peripheral CMOS is a relaxed linewidth and it is the memory array that drives NAND flash technology.
Since NAND flash was first invented, 2D floating gate planar flash has been the technology standard. In a floating gate flash memory cell, electrons are injected through a tunnel oxide to a floating gate where they are trapped. Above the floating gate is a control gate separated from the floating gate by an inter poly dielectric. Historically the inter poly dielectric has been an oxide-nitride-oxide film (ONO) although recently the inter poly film has transition to a high-k film. Figure 1. illustrates a floating gate memory cell.
Figure 1. Floating gate memory cell. Source, IC Knowledge LLC
Figure 2. illustrates the program, read and erase mechanisms.
In order to selectively program floating gate cells the control gate must couple to the floating gate of the memory cell while not coupling to the floating gate of adjacent cells. Historically one way to insure good coupling is the wrap the control gate around the floating gate but as cell spacing’s get tighter and tighter there is no longer room for the control gate to wrap around the floating gate. Also as cell spacing get tighter the control gate of one cell begins to couple to the floating gate of adjacent cells due to parasitic capacitance, see figure 3.
As NAND flash has reached low 2xnm and 1xnm feature sizes the control gate can no longer wrap around the floating gate and manufacturers have begun to implement high-k inter poly dielectrics to insure good control gate to floating gate coupling. In order to address parasitic coupling to adjacent cells air gaps have also been introduced between the memory cells.
Even with the introduction of high-k inter poly oxide and air gaps between cells, the floating gate cell is nearing the scaling limit. NAND flash linewidths have also scaled down so small that the latest 16nm generations use self-aligned quadruple patterning (SAQP) on multiple levels driving up mask counts, process complexity and cost.
2D NAND scaling
As NAND flash has scaled down mask counts slowly increased until the 3xnm generation where multipatterning became necessary. Figure 4. Illustrates 2D NAND mask count trends.
From figure 4. We can see that mask counts jumped at 21nm and again at 16nm driven by the introduction of SADP and SAQP.
Figure 5. illustrates the resulting wafer cost trend.
From figure 5. we can see that wafer costs begin to climb at 35nm with the advent of multipatterning and really take a big jump at 16nm with SAQP.
Figure 6. illustrates the memory array cell density trend.
Figure 7. combines figures 4. and 5. to produce a cost per cell trend. As in the previous two installments we have spaced out the nodes to reflect the years and more accurately portray the cost trend.
From figure 7. we can see that 2D planar NAND cost has scaled until we reach the 16nm node.
With 16nm NAND near the limit for 2D planar floating gate flash scaling and costs rapidly increasing due to the demands of fabricating such fine linewidths a new paradigm in NAND flash fabrication is needed. In 2D NAND flash the memory cells are horizontally oriented as strings of cells. The new 3D NAND flash processes literally turn the memory cell strings on end so that cells are stacked up in vertical strings.
There are four companies currently pursuing 3D NAND, Samsung, Toshiba, SK Hynix and Micron/Intel. Although there are differences in the four implementations they all share some general features.
In 3D NAND multi layers are stacked up to create the memory cells. The thickness of the layers determines gate length instead of lithography. Once all of the layers are deposited the channel is created in an opening etched down through all of the layers. The interconnect to the layers is created by a photolithography – etch – photoresist shrink – etch process where the photoresist is repeatedly shrunk to create a stair step at the periphery. Slits are also etched down through the stack.
Figure 8. illustrates a simplified cut away view of a Toshiba 3D NAND memory stack.
There are several key advantages to the 3D NAND flash processes:
- The ability to have very high density of cells per unit of horizontal area due to stacking.
- Critical dimensions are primarily set by deposition and not photolithography.
- Photolithography dimensions are relaxed versus 2D.
- Scaling to greater density is accomplished with more layers and has very little impact on the number of masks.
- 3D NAND is faster and has better endurance than 2D NAND.
In 2014 Samsung was the first company to commercially release 3D NAND with a 24 layer TCAT process. The Samsung TCAT process deposits alternating layers of oxide and nitride to create the memory stack. The nitride is later etched out and replaced with a metal stack to create the gates for charge trap memory cells. Later in the year Samsung introduced a 32 layer device. Samsung is reported to plan to increase the number of layers while maintaining the same lithography rules until something greater than one hundred layers produces a one terabit device.
Toshiba uses a Bit Cost Scalable (BiCS) process ot produce 3D NAND. The process utilizes alternating layers of oxide and polysilicon for the memory stack and the polysilicon layers become the charge trap memory cell gates. Some reports claimed Toshiba was having trouble making the “gate first” approach work but recently Toshiba announced they were sampling 48 layer devices.
The Micron/Intel flash joint venture is reported to be developing a 3D NAND solutions based on floating gate. They are the only company known to be pursuing floating gate for 3D. Parts are expected later this year.
SK Hynix is also developing a 3D NAND solution.
3D NAND scaling
3D NAND promise lower wafer cost, higher bit density and a continued scaling path of NAND. Figure 9. Illustrates a forecast of 3D NAND cost per cell trends.
As we can see from figure 9. 3D NAND offers several more generation of continued cost scaling.
Concluding remarks on Moore’s law
The industries drive to follow Moore’s law has led to decades of 35% per year cost reductions that have driven the development of new products and industry growth. After fifty years of Moore’s law we are beginning to approach the end of the line for the “law”.
DRAM is approaching fundamental limits for capacitor scaling and likely only has a few more generation of scaling left with cost reductions already slowing.
Foundry logic saw a pause in cost reduction at the 16nm/14nm node due to a pause in back end of line scaling (BEOL). At 10nm we expect some cost reduction although less than historical. At 7nm there is the opportunity to return to the historic cost reduction trend if EUV can live up to its promise. Logic likely scales to 10nm and 7nm with possible 5nm and 3nm generations to follow although scaling beyond 7nm may require a switch from FinFETs to gate alternate technologies such as TFET or nanowires.
NAND Flash is in the best shape of the three major product categories. The introduction of 3D NAND will likely provide four or five more generations of density and cost scaling.
Moore’s Law is dead, long live Moore’s Law – part 1
Moore’s Law is dead, long live Moore’s Law – part 2
Moore’s Law is dead, long live Moore’s Law – part 3
Moore’s Law is dead, long live Moore’s Law – part 4