Today was TSMC’s 2015 North American Technology Symposium. They talked about a lot of things but perhaps the most important was that they gave a lot of details of new processes, new fabs, and volume ramps.
This is the second generation of TSMC’s 16FF process. Volume production will be mid-2015, which is just one-year after 20nm volume production started. TSMC already has over a dozen tape-outs and expects to have over 50 by the end of 2015. The process has 10% better performance than competitors and 50% less power than 20nm. The ramp will be very fast. TSMC had a planned volume ramp of 5 months from zero to 50,000 wafers per month for 20nm, but they actually did it in just 3 months (which is amazing). They expect 16FF+ to be even faster since it shares a lot of equipment and learning with 20nm (in particular, the metal stack is identical). Volume production by end of 2015 is planned at 100K wpm.
TSMC said this is ahead of schedule. They have already built and yielded a 256Mb SRAM. The density of 10nm will be 2.1x that of 16nm node partially due to a new local interconnect layer and partially because they are using self-aligned spacer (aka SADP or SIT) on the metal. SRAM cell shrinks by 0.46 to 0.49. Risk production will be 4Q2015. Test chip based on ARM Cortex A-57 taped out 2 weeks ago. There is a 19% speed gain or 38% power reduction based on this test chip.
N10 is fully colored. In particular vias and dummy fill all needs to be properly colored. You can relax metal pitch selectively to increase width and lower resistance. I/Os are 1.8V but can under-drive to 1V for LPDDR4. ASIC tool flows from Synopsys and Cadence are done with Mentor due by end of May. Full-custom flows already complete for Cadence and Synopsys. Signoff flow complete for Cadence, Mentor, Synopsys (and ANSYS/Apache for EM/IR).
This is, I believe, a process newly announced today. It is a more compact version of 16FF+ aimed at the consumer marketplace. Same design rules. Simpler process, tighter process corners. Power is reduced by over 50% and the pricing is cost-competitive for mainstream markets (which I take as meaning it is cheaper than 28nm for the same design). Voltage is 0.55V. Version 1.0 collateral will be available 1Q2016 with customer tape-outs in 2H2016.
To do designs for 16FFC then standard cells need to be re-characterized, there is a new SRAM compiler, analog and interface IP should be re-characterized to check margin. All foundation IP should be available by end of 2015 with interface all available by 2Q2016.
This is a new version of the 28nm process. It is more compact with new cell libraries with 9T and 7T (versus 12T and 9T for 28HPC). It is 15% faster, better analog properties, tighter process corners. But same design rules.
To do designs for 28HPC+ then standard cells need to be re-characterized if you don’t switch to the new libraries, SRAM needs to be re-characterized, analog and interface IP should be re-characterized and may need retuning for frequency. I/Os are unchanged. All foundation IP should be available by 2Q2015 (maybe even this month) with interface all available by 4Q2015 or 1Q2016.
This is another new version of the 28nm process for ultra low power (like the already released 55ULP and 40ULP that are in production).
CoWoS for high performance in production since 2012 at 28nm. Already demonstrated with 16nm too. InFO_POP for high-volume IoT and consumer. Smallest form-factor, cost-competitive, less than 1mm thick. Ramp 2Q2016.
Fabs and Ramps
Overall capacity has CAGR of 10% from 2013 to 2017. 2015 will be 11% YoY growth.
Apparently 28nm has been in production for 5 years now, seems like only yesterday. Its D0 is <0.05 and in some cases <0.03. N28 capacity has been increasing with CAGR of 20% from 2013 to 2015. 5M 28nm wafers this year. [CORRECTION] I think this must be 5M 28nm wafers over the lifetime so far
N20 had 400,000 wafers in first year of production. D0<0.1
Specialty processes (high voltage, flash, MEMS etc) are ramping fast with 3 year CAGR of 20%. Currently 27% growing to 31%. 0.18um is still popular, increased 10% last year will increase 17% this year.
Fab 12 is the mother fab. 6 phases in production. Phase 7 10nm tool move in starts this quarter.
Fab 14 is largest fab. 6 phases in production with phase 7 ramping now.
Fab 15 phases 1-4 in production. 5/6/7 for future. Construction starting next month (presumably on phase 5).
R&D investment in 2015 will be $1.9B to $2.2B. Capex will be up 20-26% from $9.5B to $11.5-12B. TSMC runs 210 different technologies for 8800 different products. They have 11 fabs delivering 8.26M (8″ equivalent) wafers per year. They have 456 active customers, increasing by one per week.
What comes after FinFET and 10nm? Germanium fin FinFETs demonstrated, both NMOS and PMOS. First InGaAs NFET. Exploring gate-all-round nanowire technologies. Sub 30nm pitch interfonnect using trench patterning, line-end cut, metal cap fill. New barrier process may reduce resistance by 70% compared to regular shrink.
EUV source power up to 90W (ASML roadmap is 200W by Q4 of this year). 2015 also plan full demonstration of digital pattern generator module for multiple e-beam direct write. OPC no longer good enough, corners get rounded so need to go to inverse lithography technology for 10nm and beyond (basically backing out the geometry to a complex interference pattern on the mask). Directed Self Assembly <24nm line/trench patterning and <34nm hole patterning. Clearly TSMC are trying all the main ways to move lithography forward if EUV is not the answer.
You will notice there are no slides or photos. TSMC does not hand out the slides and photography and recording is banned. This is all from my notes and with so many details I am sure I may have the odd one incorrect so please tell me if I do.