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Inverse Lithography Technology – A Status Update from TSMC

Inverse Lithography Technology – A Status Update from TSMC
by Tom Dillinger on 06-02-2022 at 6:00 am
Categories: Events, Foundries, TSMC
6 Comments

ILT mask rules

“Inverse lithography technology (ILT) represents the most significant EDA advance in the last two decades.”  Danping Peng from TSMC made that assertion at the recent SPIE Advanced Lithography + Patterning Conference, in his talk entitled:  ILT for HVM:  History, Present, and Future.  This article summarizes the highlights of his insightful presentation.  Indeed, ILT has enabled improvements in the ability to print wafer-level features with improved fidelity.

ILT History

First, a brief review of the steps after design tapeout, associated with mask manufacture:

  • The mask shop applies optical proximity correction (OPC) or ILT algorithms to the mask data.
  • Mask data prep (MDP) will compose the OPC/ILT-generated data in a format suitable for the mask writer.
  • Mask writing has evolved from (an optically-based) pattern-generation shot exposure of the photoresist-coated mask blank to an e-beam based exposure. Both variable-shaped beam (VSB) and multiple-beam ask writing systems are available.  (More on this shortly.)
  • Mask inspection steps include:
    • critical dimension (CD) metrology (CD-SEM)
    • mask review using an aerial image measurement system (e.g., Zeiss AIMS)
    • mask defect repair

The mask then proceeds to the fab, where a wafer-level print will be subjected to similar steps:  CD-SEM dimensional evaluation, wafer inspection and defect analysis.

The need for mask correction algorithms is highlighted in the figure below.

As the printed dimensions on the wafer scaled with successive process nodes, the fidelity of the image – i.e., the difference between the target image and the printed wafer contour – became poor.  Corrections to the layout design data were needed.

The original approach to generating mask updates were denoted as optical proximity corrections (OPC).  Individual segments in the (rectilinear) design data were bisected at appropriate intervals, and the sub-segments were moved, typically using a rule-based algorithm.  Rectangular serifs were added at shape corners – both expanded segments at outside corners and reduced at inside corners.  (Colorful names were given to the OPC results – e.g., “hammerheads”, “dogbones”.)

Subsequently, OPC algorithms added sub-resolution assist features (SRAF) to the mask data.  These are distinct shapes from the original design, whose dimension is intentionally chosen so as not to print at the wafer photoresist resolution, but to provide the appropriate (constructive and destructive) interference due to optical diffraction at the edges of the design shapes.

As shown in the figures above and below, ILT algorithms make a fundamentally different assumption, utilizing curvilinear mask data for corrections and SRAFs.  The figure below illustrates the key differences between the edge-based nature of OPC and the pixel-based ILT algorithm.

How ILT Works

Danping used the following two figures to illustrate how ILT works.  The first figure below is a high-level flowchart, providing the comprehensive (ideal) iterative loop between mask data generation and post-etch wafer-level metrology.  (More on this full loop shortly.)

The figure below provides more detail on the ILT flow.  Two adjacent shapes are used for illustration.

A three-dimensional representation of the illumination intensity is computed.  An error function is calculated, with a weighted sum of constituent elements.  Each weight is multiplied by a factor related to the difference between the calculated print image and the wafer target across the pixel field.

The error function could include contributions from a variety of printed image characteristics:

  • nominal dimension (print-to-target difference)
  • modeled three-dimensional resist profile
  • pixel light intensity outside the target area to be suppressed
  • sensitivity to illumination dose and focus variations

Iterative optimizations are pursued to reduce the magnitude of this error function.  Note that the figure above mentions gradient-based optimization to reduce the error function calculated form a difference between a model prediction and a target – the similarities of ILT to machine learning methods are great, as Danping highlighted in the Futures portion of his talk.

Current ILT Adoption and Challenges

There have been hurdles to ILT adoption over the past two decades.  Danping reviewed these challenges, and how they are being addressed.

  • mask write time

The curvilinear (pixel-based) ILT mask data provide improved depth-of-focus over conventional OPC methods.  Yet, the corresponding data complexity results in a major increase in the e-beam shot count to write the mask, using variable size beam (VSB) technology.

Danping explained, “When ILT was first being pursued, there were no multiple beam mask writers.  As a result, it took days to expose an ILT mask with a VSB system.  Now, with multiple-beam systems, the mask write time in essentially constant, around 8 hours.” 

Note that there are “moderate constraints” applied for the ILT data generation to assist with this speed-up – e.g., minimum design rules for SRAF area/space/CD, maximum limits on the curvature of the shapes data.

  • ILT mask data generation time

“The first adoption of ILT was by memory foundries.”, Danping indicated.  “The highly repetitive nature of their layouts, with some careful crafting, results in a reduced number of repeating patterns.” 

ILT adoption for logic designs has been slower.  Danping elaborated on some of the challenges:

    • long computational runtime (“20X slower than OPC”)
    • mask data rules checking technology for curvilinear edges has lagged
    • improvements in exposure systems have improved image resolution (e.g., 193 to 193i) and dose uniformity, reducing the ILT advantages

ILT algorithms for model generation and error function + gradient computation is dominated by matrix operations.  To address the runtime challenge, ILT code has been ported to GPU-based computation resources.  This provides “a 10X speed-up over strictly CPU-based computation”, according to Danping.

To address the mask data validation challenge, the SEMI Curvilinear Task Force is working on a data representation that will serve as a standard format for model interchange.  (This is also driven by the curvilinear design layout data associated with silicon photonics structures.)  The figure below illustrates new “rule definitions” that will be part of mask data checking.

Danping provided the following observation on the market opportunity for ILT relative to improvements in exposure systems, “ILT can be used to squeeze more performance from an existing tool.”  In that sense, ILT may enable extended utilization of existing scanners.

Danping shared a forecast that “Both EUV and 193i masks will commonly incorporate curvilinear shapes in 2023.”  (Source:  eBeam Initiative)

ILT Future

Danping offered three forecasts for ILT technology.

  • adoption of deep learning techniques

As mentioned above, the ILT algorithm shares a great deal in common with the computation and optimization techniques of deep neural network methods.  The figure below illustrates how deep learning could be adopted.

“A trained deep learning model could be used to generate mask data, followed by a small number of ILT iterations.  ILT mask data could be derived in 15% of the previous runtime.”, Danping mentioned.

  • increased use of curvilinear design data

In addition to silicon photonics structures, the opportunity to use curvilinear data directly in circuit layouts at advanced process nodes may soon be adopted.  (Consider the case where metal “jumpers” are used on layer Mn+1 to change routing tracks for a long signal on layer Mn.)  The industry support for curvilinear data representation would enable this possibility, although it would also have a major impact on the entire EDA tool flow.

  • a full “inverse etch technology” (IET) flow to guide ILT

An earlier figure showed a “full loop” flow for mask data generation, incorporating post-etch results.  Rather than basing the ILT error function on computational models of the resist expose/develop profile, the generation of the cost function would be derived from the final etched material image model, as illustrated below.

(DOM:  dimension of mask;  ADI:  after photoresist develop inspection;  AEI:  after etch inspection)

Significant effort would be needed to construct the “digital twin” models for etch processes.  However, the benefits of a comprehensive mask data-to-process flow optimization would be great.

Summary

ILT will clearly expand beyond its current (memory-focused) applications.  The industry efforts to support a standard for efficient and comprehensive curvilinear data representations – for both mask and design data – will help to accelerate the corresponding EDA and fabrication equipment enablement.  As Danping put it, “It is not a question of if, but when and how many layers will use ILT.”

-chipguy

Also Read:

TSMC N3 will be a Record Setting Node!

Intel and the EUV Shortage

Can Intel Catch TSMC in 2025?

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TSMC N3 will be a Record Setting Node!

TSMC N3 will be a Record Setting Node!
by Daniel Nenni on 05-19-2022 at 6:00 am
Categories: Events, Foundries, TSMC
5 Comments

waferr007 2518 Q9Wf 0

With the TSMC Technical Symposium coming next month there is quite a bit of excitement inside the fabless semiconductor ecosystem. Not only will TSMC give an update on N3, we should also hear details of the upcoming N2 process.

Hopefully TSMC will again share the number of tape-outs confirmed for their latest process node. Given what I have heard inside the ecosystem, N3 tape-outs will be at a record setting number. Not only has Intel joined TSMC for multi-product high volume N3 production, it has been reported that Qualcomm and Nvidia will also use N3 for their leading edge SoCs and GPUs. In fact, it would be easier to list the companies that will not use TSMC for 3nm but at this point I don’t know of any. It is very clear that TSMC has won the FinFET battle by a very large margin, absolutely.

“The most outstanding news of TSMC in 2021 was the success in attracting more new business from Intel, while being able to maintain great relationships with existing customers such as AMD, Qualcomm and Apple. With its 3 nm N3 entering volume production later in 2022 with good yield and 2 nm N2 development being on track for volume production in 2025, TSMC is expected to continue its technology leadership to support its customer innovation and growth. Thanks to the demand of bleeding-edge technologies, TSMC’s foundry leadership position seems to have become even more concrete in recent years.”

Samuel Wang, analyst with Gartner, from their recent analyst report: “Market Share Analysis: Semiconductor Foundry Services, Worldwide, 2021” that went live on May 9, 2022.

Now that live events have started up again in Silicon Valley the information flow inside the semiconductor ecosystem has returned to pre pandemic levels. I have attended (6) live semiconductor events thus far in 2022 and have several more to go before the biggest foundry event The 2022 TSMC Technology Symposium which kicks off at the Santa Clara Convention Center on June 16 followed by events in Europe (6/20), China (6/30), and Taiwan (6/30).

SemiWiki has covered the TSMC events for the past 11 years and we will have bloggers attending this year as well. This is the number one networking event for TSMC customers, partners, and suppliers so I can assure you there will be a lot to write about.

Here is the most recent update on technology development from TSMC:

  • TSMC’s 3nm technology development is on track with good progress, and the company has developed complete platform support for HPC and smartphone applications. TSMC N3 is entering volume production in the second half of 2022, with good yield.
  • TSMC N3E will further extend its 3nm family, with enhanced performance, power, and yield. The Company also observed a high level of customer engagement at N3E, and the volume production for N3E is scheduled for one year after N3
  • Faced with the continuous challenge to significantly scale up semiconductor computing power, TSMC has focused its R&D efforts on contributing to customers’ product success by offering leading-edge technologies and design solutions. In 2021, the company started risk production of 3nm technology, the 6th generation platform to make use of 3D transistors, while continuing the development of 2nm, the leading-edge technology in the semiconductor industry today. Furthermore, the company’s research efforts pushed forward with exploratory studies for nodes beyond 2nm. TSMC’s 2nm technology has entered the technology development phase in 2021, with development being on track for volume production in 2025.

TSMC also introduced N4P process in October 2021, a performance-focused enhancement of the 5nm technology platform. N4P delivers an 11% performance boost over the original N5 technology and a 6% boost over N4. Compared to N5, N4P will also deliver a 22% improvement in power efficiency as well as a 6% improvement in transistor density.

TSMC introduced N4X process technology at the end of 2021, which offers a performance boost of up to 15% over N5, or up to 4% over the even faster N4P at 1.2 volt. N4X can achieve drive voltages beyond 1.2 volt and deliver additional performance. TSMC expects N4X to enter risk production by the first half of 2023. With N5, N4X, N4P, and N3/N3E, TSMC customers will have multiple and compelling choices for power, performance, area, and cost for their products.

Bottom line: This will be one of the more exciting TSMC Technical Symposiums. TSMC N2 has been under NDA while the IDM foundries have been leaking details about their upcoming 2nm processes. This is a classic marketing move, when you don’t have a competing product today, talk about tomorrow.

One thing we should all remember is that all of the leading semiconductor companies, with the exception of Samsung, are collaborating with TSMC. The TSMC ecosystem consists of 100s of customers, partners, and suppliers and it is like no other. If you think another foundry will have a higher yielding 2nm process that can support a wide range of products you would be wrong.

Also read:

Can Intel Catch TSMC in 2025?

TSMC’s Reliability Ecosystem

Self-Aligned Via Process Development for Beyond the 3nm Node

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Intel and the EUV Shortage

Intel and the EUV Shortage
by Scotten Jones on 04-13-2022 at 10:00 am
Categories: Foundries, Intel Foundry, Lithography, Samsung Foundry, Semiconductor Services, TechInsights, TSMC
12 Comments

Slide1

In my “The EUV Divide and Intel Foundry Services” article available here, I discussed the looming EUV shortage. Two days ago, Intel announced their first EUV tool installed at their new Fab 34 in Ireland is a tool they moved from Oregon. This is another indication of the scarcity of EUV tools.

I have been tracking EUV system production at ASML to-date and forecasted output looking forward. I have also been looking at fabs that have been built and equipped and fab announcements to estimate the future requirement for EUV tools.

My approach is as follows:
  • List out each EUV capable fab by company with process type/node and capacity by year. I estimate how many EUV exposures are required for each process and convert this to an EUV layer count forecast by year (exposures x capacity).
  • For each year I look at the type(s) of EUV tools ASML produces and estimate the throughput by tool type for logic and memory processes.
  • Outset the required tools by time to account for the time between a tool delivery and the tool being in production.
Some notes about demand:
  • Intel currently has 3 development fabs phases that are EUV capable and 1 EUV capable production fab although only the development fab has EUV tools installed. Intel is building 8 more EUV capable production fabs.
  • Micron Technology has announced they are pulling in EUV from the one delta node to one gamma. Micron’s Fab 16-A3 in Taiwan is under construction to support EUV.
  • Nanya has talked about implementing EUV.
  • SK Hynix is in production of one alpha DRAM using EUV for approximately 5 layers and have placed a large EUV tool order with ASML.
  • Samsung is using EUV for 7nm and 5nm logic and ramping up 3nm. Samsung also has 1z DRAM in production with 1 EUV layer and 1 alpha ramping up with 5 EUV layers. Fabs in Hwaseong and Pyeongtaek have EUV tools with significant expansion in Pyeongtaek underway and the planned Austin logic fab will be EUV.
  • TSMC has fab 15 phases 5, 6, and 7 running 7nm EUV processes. Fab 18 phase 1, 2, and 3, are running 5nm with EUV. 5nm capacity ended 2021 at 120k wpm and has been projected to reach 240k wpm by 2024. Fab 21 in Arizona will add an additional 20k wpm of 5nm capacity. 3nm is ramping in Fab 18 phases 4, 5, and 6 and is projected to be a bigger node than 5nm. Fab 20 phases 1, 2, 3, and 4, are in the planning stages for 2nm and another 2nm site is being discussed.

Based on all of these fabs and our estimated timing and capacity we get figure 1.

Figure 1. EUV Supply and Demand.

 Figure 1 leads to a couple of key observations:

  • There will be more demand for EUV tools than supply in 2022, 2023, and 2024. Our latest forecast is a shortage of 18 tools in 2022, 12 tools in 2023 and 20 tools in 2024.
  • Looking at the logic companies where the bulk of EUV demand is, TSMC has the most EUV systems with roughly one half of the systems in the world, Samsung is next and then Intel. Of the three companies Intel will likely be the most constrained by the supply of EUV tools. It wasn’t that long ago that Intel was pushing out EUV tool orders, likely a mistake they wish they could take back.

In summary, over at least the next three years, leading edge EUV based capacity will be constrained by the scarcity of EUV tools with Intel likely to be hardest hit.

Also read:

Can Intel Catch TSMC in 2025?

The EUV Divide and Intel Foundry Services

Samsung Keynote at IEDM

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Can Intel Catch TSMC in 2025?

Can Intel Catch TSMC in 2025?
by Scotten Jones on 04-11-2022 at 6:00 am
Categories: FinFET, Foundries, Intel Foundry, Lithography, Semiconductor Services, TechInsights, TSMC
11 Comments

Slide6

At the ISS conference held from April 4th through 6th I presented on who I thought would have the leading logic technology in 2025. The following is a write up of that presentation.

ISS was a virtual conference in 2021 and I presented on who currently had logic leadership and declared TSMC the clear leader. Following that conference, I did a lot of calls for investment firms, and I was often asked when Intel would catch TSMC, my answer was unless TSMC stumbled, never.

A year later the foundries are stumbling, and Intel is accelerated, can Intel catch up?

I reviewed some Intel history, discussed their leadership throughout the 2000s and then how in the 2010s they began to fall behind, I discussed why I thought this happened.

I have previously published on Intel’s issues here.

The bottom line is 2014 through 2019 Samsung and TSMC each introduced 4 nodes while Intel introduced 2, the Intel nodes were bigger individual density jumps but when you chain together the 4 foundry jumps, they increased density more than Intel and took the lead. Figure 1. summarizes this.

Figure 1. Foundries Versus Intel in the 2010s.

Figure 1 only illustrates the “nodes” from Intel, they weren’t standing still, for 14nm they released 5 versions all with the same density but with progressively improving performance and for 10nm they released 4 versions, once again with the same density but improving performance (note the last version has now been renamed 7nm).

By 2020 Samsung and TSMC both had 5nm in production and compared to Intel 10nm they are denser processes. TSMC had taken a lager jump from 7nm to 5nm then Samsung and was the clear leader with the densest process, smallest SRAM cell size and the industries first silicon germanium FinFET. Figure 2. summarizes this.

Figure 2. 2020 Comparison.

In 2021 the foundries have slowed down.

Samsung 3nm has encountered yield issues and we believe in 2022 their 3GAE (early) process will be used almost exclusively for internal products with 3GAP (performance) being released to external customers in 2023. Samsung chose to go to Horizontal Nanosheets (HNS) for 3nm (a type of gate all around process Samsung calls Multibridge). I believe HNS production issues are still being worked out and Samsung’s interest in being first to HNS has led to delays and poor yields.

TSMC did risk starts of their FinFET based 3nm process in 2021 but production is now pushed to late 2022 with products in the industry in 2023. In 2019 TSMC had risk starts of 5nm and by late 2020 iPhones were shipping with TSMC 5nm parts, for 3nm we won’t see iPhones until 2023. TSMC has also reduced the density for this process from an original 1.7x target to ~1.6X with reduced performance targets.

While Samsung and TSMC were experiencing delays, Intel announced, “Intel Accelerated”, an aggressive roadmap of 4 nodes in 4 years. This is truly accelerated when you consider 14nm took 3 years and 10nm took 5 years. I was frankly skeptical of this when it was announced but at the recent investors event Intel is pulling in the most advanced 18A process from 2025 to 2024!

Our view from now to 2025 is as follows:

2022 – Intel 4nm process, Intel’s first EUV use with a 20% performance improvement over 7nm. Intel had formerly talked about a 2X density improvement for this generation but is now just saying a “significant density improvement”, we are estimating 1.8X. Samsung 3nm will likely be for internal use only with a 1.35X density improvement, 35% better performance at the same power and 50% lower power at the same performance. The density improvement is not very impressive but the performance and power improvements are, likely due to adoption HNS. TSMC 3nm is FinFET based and will provide an ~1.6X density improvement with 10% better performance at the same power and 25% lower power at the same performance.

2023 – Intel 3nm process with 18% better performance, denser libraries and more EUV use. We estimate a 1.09X density improvement making this more of a half node. Samsung 3GAP should be available to external customers and TSMC 3nm parts should appear in iPhones.

2024 – in the first half Intel 20A (20 angstrom = 2nm) process is due with a 15% performance improvement. This will be Intel’s first HNS (they call it RibbonFET) and they will also introduce back side power delivery (they call this PowerVia). The backside power delivery addresses IR power drops while making front side interconnect easier. We are estimating a 1.6X density improvement. In the second half of 2024 Intel’s 18A process is due with a 10% performance improvement. We are estimating a 1.06X density improvement making this another half node. This process has been pulled in from 2025 and Intel says they have delivered test devices to customers.

2025 – Samsung 2nm is due in late 2025, we expect it to be a HNS and because it will be Samsung’s third generation HNS (counting 3GAE as the 1st generation and GAP as the 2nd generation) and their previous generations have been relatively less dense we are forecasting a 1.9X density jump. TSMC has not announced their 2nm process yet other than to say they expect to have the best process in 2025. We may see 2nm in 2024 but for now we have it placed in 2025, we expect a HNS process and are estimating a 1.33X density improvement. We believe the density improvement will be modest because it is TSMC’s first HNS and because the 3nm process is so dense that further improvements will be more difficult.

Figure 3 illustrates how Intel may “flip the script” on the foundries by doing 4 nodes while the foundries do 2.

Figure 3. Density jumps.

We can now look at how Intel, Samsung, and TSMC will compare in density out to 2025. We also added IBM’s 2nm research device based on their 2nm announcement. Figure 4. presents both density versus year and node.

Figure 4. Transistor Density Trends.

 From figure 4 we expect TSMC to maintain the density lead through 2025.

The most complex part of our analysis is illustrated in figure 5 where we compare performance. It is very difficult to compare processes to each other for performance without having the same design run on different processes and this rarely happens. The way we generated this plot is as follows:

  • The Apple A9 process was run in both Samsung 14nm and TSMC 16nm and Tom’s hardware found the same performance for both versions, we have normalized performance at this node to 1 for both Samsung and TSMC.
  • From the 14/16nm node through 3nm we have used the companies announced performance improvements to plot relative performance. For 2nm we have used our own projections.
  • We don’t have any designs that ran on Intel processes and either Samsung or TSMC. However, AMD and Intel both make X86 microprocessors and AMD microprocessors on TSMC 7nm process have competed with Intel 10nm Superfin processors with similar performance and we have set Intel 10SF to the same performance as TSMC 7nm. This is not ideal and assumes that both companies have done an equally good job on design but is the best available comparison. We have then scaled all the other Intel nodes from the 10SF based on Intel’s announcements.
  • Once again, we have place IBM’s 2nm on this chart based on their 2nm announcement.

Figure 5. Relative Performance Trends.

 Our analysis leads us to believe Intel may take the performance lead both on a year basis and a node basis. This is consistent with Intel’s stated goal of taking the “performance per watt lead”. Assuming TSMC is referring to density their statement that they will have the best process in 2025 could also be true.

In conclusion we believe Intel has been able to significantly accelerate their process development at a time when the foundries are struggling. Although we don’t expect Intel to regain the density lead over the time period studied, we do believe they could retake the performance lead. We should get another good read on progress by the end of 2022 when we see whether Intel 4nm comes out on time.

Also Read:

TSMC’s Reliability Ecosystem

The EUV Divide and Intel Foundry Services

Intel Discusses Scaling Innovations at IEDM

Samsung Keynote at IEDM

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TSMC’s Reliability Ecosystem

TSMC’s Reliability Ecosystem
by Tom Dillinger on 04-06-2022 at 10:00 am
Categories: Events, Foundries, TSMC

AC accelerated stress conditions

TSMC has established a leadership position among silicon foundries, based on three foundational principles:

  • breadth of technology support
  • innovation in technology development
  • collaboration with customers

Frequent SemiWiki readers have seen how these concepts have been applied to the fabrication and packaging technology roadmaps, which continue to advance at an amazing cadence.  Yet, sparse coverage has typically been given to TSMC’s focus on process and customer product reliability assessments – these principles are also fundamental to the reliability ecosystem at TSMC.

At the recent International Reliability Physics Symposium (IRPS 2022), Dr. Jun He, Vice-President of Corporate Quality and Reliability at TSMC, gave a compelling keynote presentation entitled:  “New Reliability Ecosystem: Maximizing Technology Value to Serve Diverse Markets”.  This article provides some of the highlights of his talk, including his emphasis on these principles.

Technology Offerings and Reliability Evaluation

The figures above highlight the diverse set of technologies that Dr. He’s reliability team needs to address.  The reliability stress test methods for these technologies vary greatly, from the operating voltage environment to unique electromechanical structures.

Dr. He indicated, “Technology qualification procedures need to be tailored toward the application.  Specifically, the evaluation of MEMS technologies necessitates unique approaches.  Consider the case of an ultrasound detector, where in its end use the detector is immersed in a unique medium.  Our reliability evaluation methods need to reflect that application environment.”

For more traditional microelectronic technologies, the reliability assessments focus on accelerating defect mechanisms, for both devices and interconnect:

  • hot carrier injection (HCI)
  • bias temperature instability (NBTI for pFETs, PBTI for nFETs)
  • time-dependent dielectric breakdown (TDDB)
  • electromigration (for interconnects and vias)

Note that these mechanisms are highly temperature-dependent.

As our understanding of the physics behind these mechanisms has improved, the approaches toward evaluating their impact to product application failure rates have also evolved.

Dr. He commented, “Existing JEDEC stress test standards are often based on mechanism acceleration using a DC Vmax voltage.  However, customer-based product qualification feedback did not align with our technology qualification data.  Typically, the technology-imposed operating environment restrictions were more conservative.”

This is of specific interest to high-performance computing (HPC) applications, seeking to employ boost operating modes at increased supply voltages (within thermal limits).

Dr. He continued, “We are adapting our qualification procedures to encompass a broader set of parameters.  We are incorporating AC tests, combining Vmax, frequency, and duty cycle variables.”

The nature of “AC recovery” in the NBTI/PBTI mechanism for device Vt shift has been recognized for some time, and is reflected in device aging models.  Dr. He added, “We are seeing similar recovery behavior for the TDDB defect mechanism.  We are aggressively pursuing reliability evaluation methods and models for AC TDDB, as well.”

The figure above illustrates the how the Vt shift due to BTI is a function of the duty cycle for the device input environment, as represented by the ratio of the AC-to-DC Vt difference.  The figure also highlights the newer introduction of a TDDB lifetime assessment for high-K gate dielectrics, as a function of input frequency and duty cycle.

Parenthetically, Dr. He acknowledged that end application product utilization can vary widely, and that AC reliability testing makes some usage assumptions.  He indicated that TSMC works with customer to establish appropriate margins for their operating environment.

Reliability Evaluation of New Device Types

TSMC has recently added resistive RAM (RRAM) and magneto-resistive RAM (MRAM) IP to their technology offerings.

The unique physical nature of the resistance change in the storage device for these technologies necessitates development of a corresponding reliability evaluation procedure, to establish retention and endurance specifications.  (For the MRAM technology, the external magnetic field immunity specification is also critical.)

For both these technologies, the magnitude and duration of the write current to the storage cell is a key design parameter.  The maximum write current is a crucial reliability factor.  For the MRAM example, a high write current through the magnetic tunnel junction to set/reset the orientation of the free magnetic layer in the storage cell degrades the tunnel barrier.

TSMC collaborates with customers to integrate write current limiting circuits within their designs to address the concern.  The figure below illustrates the write current limiter for the RRAM IP.

TSMC and Customer Collaboration Reliability Ecosystem

In addition to the RRAM and MRAM max write current design considerations, Dr. He shared other examples of customer collaborations, which is a key element of the reliability ecosystem.

Dr. He. shared the results of design discussions with customers to address magnetic immunity factors – the figure below illustrates cases where the design integrated a Hall effect sensor to measure the local magnetic field.  The feedback from the sensor can be used to trigger corrective actions in the write cycle.

The customer collaboration activities also extend beyond design for reliability (DFR) recommendations.  TSMC shares defect pareto data with customers.  Correspondingly, the TSMC DFR and design-for-testability (DFT) teams will partner with customers to incorporate key defect-oriented test screens into the production test flow.

Dr. He provided the example where block-specific test screens may be appropriate, as illustrated below.

Power management design approaches may be needed across the rest of the design to accommodate block-level test screens.

The figure below depicts the collaboration model, showing how customer reliability feedback is incorporated into both the test environment and as a driver for continuous improvement process (CIP) development to enhance the technology reliability.

Summary

At the recent IRPS, TSMC presented their reliability ecosystem, encompassing:

  • developing unique reliability programs across a wide breadth of technologies (e.g., MEMS)
  • developing new reliability methods for emerging technologies (e.g., RRAM, MRAM)
  • sharing design recommendations with customers to enhance final product reliability
  • collaborating closely with customers on DFR issues, and integrating customer feedback into DFT screening procedures and continuous improvement process focus

Reflecting upon Dr. He’s presentation, it is no surprise that these reliability ecosystem initiatives are consistent with TSMC’s overall principles.

-chipguy

Also read:

Self-Aligned Via Process Development for Beyond the 3nm Node

Technology Design Co-Optimization for STT-MRAM

Advanced 2.5D/3D Packaging Roadmap

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The EUV Divide and Intel Foundry Services

The EUV Divide and Intel Foundry Services
by Scotten Jones on 03-23-2022 at 10:00 am
Categories: Foundries, Intel Foundry, Lithography, Samsung Foundry, Semiconductor Services, TechInsights, TSMC
37 Comments

Intel IDM 2.0 Process Roadmap
The EUV Divide

I was recently updating an analysis I did last year that looked at EUV system supply and demand, while doing this I started thinking about Intel and their Fab portfolio.

If you look at Intel’s history as a microprocessor manufacturer, they are typically ramping up their newest process node (n), in volume production on their previous node (n-1) and ramping down the node before that (n-2 node). They don’t typically keep older nodes in production, for example, last year 10nm was n, 14nm was n-1 and 22nm was n-2. Intel had some 32nm capacity in Fab 11X but that has now been converted to a packaging Fab. This contrasts with someone like TSMC that built their first 130nm – 300mm fab in 2001 and is still running it plus their 90nm, 65nm, 40nm and 28nm fabs as well.

By the end of 2022 Intel should be ramping up their 4nm node, then in 2023 their 3nm node, and in 2024 their 20A (2nm) and 18A (1.8nm) nodes should ramp up. All of those are EUV based nodes and it would seem reasonable that by the end of 2024 Intel would have little use for non-EUV based processes for microprocessor production since their 7nm/10nm non-EUV nodes would be n-4/n-5 depending on how you treat 10nm/7nm.

If I look at Intel’s current and planned Fab portfolio, there are EUV capable fabs and older fabs that are unlikely to ever be used for EUV, in fact EUV tools require an overhead crane and many of Intel’s older fabs would likely require significant structural modifications to accommodate this, plus Intel is building 9 EUV based production fabs.

The following is a site by site look at Intel’s fabs:

  • New Mexico – Fab 11X phases 1 and 2 are Intel’s oldest production fabs and they are being converted to packaging Fabs. 11X-3D may continue to operate for 3D Xpoint. Intel recently discussed two more generations of 3D Xpoint and this is currently the only place to make it.
  • Oregon – Fab D1X phases 1, 2 and 3 now lead all of intel’s EUV based development and early production. Fabs D1C/25 and D1D are older development/production fabs that are unlikely to be converted to EUV and are currently being used for non-EUV production.
  • Arizona – Fabs 52 and 62 are EUV fabs under construction. Fab 42 is currently running non-EUV nodes but it was built as a EUV capable Fab and will likely be used for EUV someday. Fabs 12 and 32 are production fabs running non-EUV nodes and will likely never be converted to EUV.
  • Ireland – Fab 34 is an EUV fab under construction with equipment currently being moved in, this will likely be Intel’s first 4nm EUV node production site. Fabs 24 phases 1 and 2 are non-EUV production sites and will likely never be used for EUV (unless they get combined with Fab 34 at some point).
  • Israel – Fab 38 is an EUV fab under construction and will be a 4nm EUV node production site. Fabs 28 phases 1 and 2 are non-EUV node production and will likely never be used for EUV (unless they get combined with Fab 34 at some point).
  • Ohio – Silicon Heartland EUV based fabs 1 and 2 are in the planning stage.
  • Germany – Silicon Junction EUV based fabs 1 and 2 are in the planning stage.

In summary Intel is in various stages of running, building, or planning the following EUV based fabs, D1X phases 1, 2 and 3, Fabs 42, 52, and 62, Fab 34, Fab 38, Silicon heartland 1 and 2 and Silicon Junction 1 and 2. That is 3 development fabs/phases and 9 EUV based production fabs.

For non-EUV fabs still running, Intel has D1C/25, D1D, Fabs 12 and 32, Fab 24 phases 1 and 2, and Fab 28 phases 1 and 2. That is 8 non-EUV production Fabs. This really puts into perspective why Intel would want to get into the foundry business and support trailing edge processes. All these fabs can be used to produce any of Intel’s non EUV 10nm/7nm and larger processes plus likely with reasonable changes in equipment sets any of the processes they will be acquiring from the Tower acquisition.

Déjà vu all over again

Yogi Bera is famous for being humorously quotable and one of his famous quotes was “it is Déjà vu all over again”.

The last time Intel tried to get into the foundry business they failed to gain much traction. Foundry was still a second-class citizen at Intel, they didn’t have the design eco system and eventually exited the foundry business. One of the things that bothered me about Intel’s effort and in my opinion sent a message to foundry customers that foundry was second class was that Intel would develop a new process node, for example 32nm, they would introduce a high performance version for internal use and then a year later introduce the foundry (SOC) version.

Recently I saw an interview with Pat Gelsinger where he talked about 4nm being an internal process for Intel and then 3nm being the foundry version. 3nm is currently expected to come out approximately a year after 4nm. He then talked about 20A as an internal process and 18A as the foundry version. 18A is due to come out 6 to 9 months after 20A. I don’t think foundry customers will accept always being 6 to 12 months behind the leading edge and I think it sends the wrong message. He did say if a foundry customer really wanted to use 4nm they could, but he seemed to view 4nm and 20A as processes that should be tested internally before the next version is released more widely.

I do think Intel has an interesting opportunity. There is a shortage of foundry capacity at the trailing edge where Intel will likely be freeing up a lot of fab capacity and there is a shortage at the leading edge as well. In addition to that, there is a need for a second source at the leading edge. Samsung has a long history of over promising and under delivering on technology and yield. Companies like Qualcomm have repeatedly tried to work with Samsung, so they aren’t wholly dependent on TSMC and have been repeatedly forced back to TSMC. The latest example is the Qualcomm’s Snapdragon 8 gen 1 that is reported to have only 35% yield on Samsung’s 4nm node. If Intel can execute on their technology roadmap in a consistent basis with good yield, they can likely pick up a lot of second source and maybe even some primary source leading edge business particularly at Samsung’s expense. I could even see a company like Apple giving Intel some designs to strengthen their negotiating position with TSMC. I wouldn’t expect MediaTek, a Taiwan company located near TSMC, or AMD or NVDIA due to competitive concerns to work with Intel, but never say never.

EUV  shortage

As I mentioned at the outset it is a EUV supply and demand analysis I have been doing that triggered EUV gap ideas. As I outlined above Intel plans to build out and equip 9 EUV based Fabs. At the same time TSMC 5nm is widely believed to have ended 2021 at 120 thousand wafer per month capacity. TSMC has announced they expect to double the end of 2021 capacity on 5nm, by the end of 2024 and that is before the Arizona 5nm fab comes online. TSMC has talked about 3nm being an even bigger node than 5nm. TSMC has also started planning on a 4 phase 2nm fab with a second site in discussion. Samsung started using EUV for one layer on their 1z DRAM and then 5 layers on their 1a DRAM. Samsung is planning a new EUV based logic fab in Texas and is building out logic and DRAM capacity in Pyeongtaek. SK Hynix has started using EUV for DRAM, Micron has pulled in their DRAM EUV use from the delta to gamma generation and even Nanya is talking about using EUV for DRAM. This begs the question, will there be enough EUV tools available to support all these needs and my analysis is that there won’t.

In fact, I believe there will be demand for 20 more EUV tools than ASML can produce each of the next 3 years. To put that is perspective, ASML shipped 42 EUV systems in 2021 and is forecasting 55 system in 2022. Interestingly I saw a story today where Pat Gelsinger commented that he is personally talking to the CEO of ASML about system availability and admitted that EUV system availability will likely gate the ability to bring up all the new fabs.

I think another impact the EUV system shortage will drive is a different view of what layers to use EUV on. If a layer is currently done with multi-patterning more complex than double patterning EUV is generally cheaper. EUV also enables simpler design rules, more compact layouts, and potentially better performance. EUV will be even more important as the switch is made to horizontal nanosheets. I believe companies will be forced to prioritize EUV use to the layers where it has the most impact and continue to use multi-patterning for other layers.

Also Read

Intel Evolution of Transistor Innovation

Intel Discusses Scaling Innovations at IEDM

Intel 2022 Investor Meeting

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TSMC Earnings – The Handoff from Mobile to HPC

TSMC Earnings – The Handoff from Mobile to HPC
by Doug O'Laughlin on 01-20-2022 at 10:00 am
Categories: Events, Fabricated Knowledge, Semiconductor Services, TSMC
4 Comments

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Hello! The most important semiconductor company in the world reported earnings last night. It’s been something of a tradition to post Taiwan Semiconductor Company (TSMC) earnings posts not behind my paywall, and I think that I’m going to continue that to kickoff each earnings season.

There are so many threads in the TSMC call that I want to talk about, but the big one that I think we will look back on 2022 for TSMC is that this is the year HPC will become the largest part of the business. Let’s expand.

TSMC’s current business mix

Smartphones and HPC are neck and neck in the largest buckets for TSMC, but HPC is growing faster. The reason for sluggish smartphone growth was laid out pretty well by TSMC, and that’s volume growth in smartphones has topped out.

Yes, I think — let me add. The global smartphone unit growth last year is about 6%. So some of the — you see some of the company smartphone revenue may grow, it could be due to the pricing. But we — our pricing strategy, as you understand, is strategic, not optimistic. So we’ll grow with the smartphone units in our business.

Well TSMC just guided for “high 20s” growth, and long-term growth of 15-20% CAGR. They additionally guided to an accelerating 2022, and strong sequential growth into Q1. Given that they think that their business will grow in-line smartphone units, the only logical growth driver is HPC. I did some pretty simple math to back out what the HPC segment should look like given their assumptions on growth.

Let me answer the platform question. In 2022, we expect the HPC and automotive to grow faster than the corporate average. IoT, similar. Smartphones close to the corporate average. That’s the platform growth.

I’m a bit more bearish on smartphones growing 20%+ unit growth so let’s say smartphones grow at 15% next year, and DCE / Other grows at 10% as well. I grew automotive at 50% and IoT at ~28% – and the result is that HPC revenue crosses over smartphones in 2022. I use HPC revenue as the plug to then hit the ~28% revenue number. It looks like this is the year HPC is finally larger than Smartphones at TSMC.

For the longest time, I have believed that the largest incremental dollar pool of revenue growth will be HPC. It’s nice to see it come true and TSMC confirms that this is their belief as well. I first wrote about when I suspected meaningful growth in the data center in 2022 after Facebook’s earnings. I got it confirmed shortly thereafter by AIchip’s results. I had a suspicion that data center would be strong, but hearing the largest fab in the world expect something akin to ~40%+ growth in this segment is pretty mind-boggling even to a huge bull like me.

Another point to the leadership of the data center going forward is that HPC is starting to adopt the smaller nodes faster than smartphones, which used to be the premier first adopters of TSMC’s newest node. In the past, HPC would adopt the newest node a year after smartphone, but now HPC is in the driver seat and will be adopting N3 at the same time smartphone is. Beyond just node adoption, I’m pretty bullish on data center exposed stocks like Marvell and Nvidia.

Speaking of Marvell and Nvidia one of the questions on the call was “how can you grow your revenue faster than your fabless customer’s expected revenue growth”. TSMC answered that they believe it’s pricing and share gains.

This is C.C. Wei. Actually, the growth in 2022 is all the above you just mentioned. It’s a share gain, it’s the pricing and also its a unit growth. Did I answer your question?

Part of this is that Intel is starting to outsource to TSMC and that foundry likely will grow faster than memory this year. But I have a hard time believing another obvious answer is that the fabless estimates are too low.

Given that TSMC just guided to accelerating revenue (25% 2021 growth to 28%+ 2022 growth) and has over 50% of global market share, I have a hard time believing that the industry is going to meaningfully decelerate while TSMC revenue explodes. The numbers don’t reconcile. And that is why I believe that the fabless companies’ revenue estimates are likely a bit too low. Also that their 9% industry growth number is likely too low. Getting the theme here?

I believe that 2022 is going to be another strong year, and that almost every fabless company’s numbers will be revised higher. Let’s turn next to the capex side of the equation.

TSMC Expects to Spend $40-44B on Capex

Not only was growing faster for longer a surprise but the $40-44b capex was a real shocker. For context, the most bullish estimate on the street was at ~$40 billion. The upside is now the new downside case. Given that WFE grew by ~40% last year, and TSMC grew capex by ~77% in 2021 over 2020, this is pretty meaningful growth. In absolute terms, they are adding more spending in 2022 than in 2021. But of course, this is a deceleration on a larger base.

I think that the preliminary read-through is that WFE is going to have yet another good year. I believe that WFE likely is more to the tune of 20% growth than to 10% growth. Speaking of 10% growth – this estimate by SEMI came out on January 11th called for 10% growth and after TSMC’s spending estimates it already seems like this will be false. 2 days and it’s already out of date! The true number is going to be higher.

As we discussed on the VLSI semicap comparison of numbers bottom-up to top-down, it seems like estimates need to move higher. I think this is great for semicap broadly (surprise!). If you’re a long-time reader of the substack, one of the core beliefs is that the rising capital intensity of making a semiconductor accretes to fabs and even more so to semicap companies (ASML, LRCX, AMAT, KLAC, TOELY, etc).

This is just another indication that the thesis is correct given that Capex is growing faster than revenue. Which brings me to an interesting question – how could TSMC ever support this kind of spending indefinitely? The answer is that they are either utterly wrong about their growth and are going to throw the entire market into overcapacity, or that demand is still being underestimated. I believe that it’s the latter, as I wrote in my cyclical to the secular thought experiment. I believe that TSMC believes this as well, and given how they are investing and guiding, I want to call this TSMC’s bold bet.

Growing for Longer – TSMC’s Bold Bet

A recurring theme of the analysts calls with TSMC is that every quarter analysts pepper management with “how can you maintain the margin with this investment?” and “you’re spending a lot on capex will this ever normalize?” questions. The answer that TSMC answers each quarter is somewhere along the lines of “We are going to grow trust us”. This first long-term guidance in a while is an indication of that.

We expect our long-term revenue to be between 15% and 20% CAGR over the next several years in U.S. dollar terms, of course, fueled by all 4 growth platform which are smartphone, HPC, IoT and automotive.

The staggering thing I want to point out to you is their 10-year revenue growth CAGR is 14%. That’s the kind of growth that got them to the largest fab in the industry, yet their long-term revenue guide is now actually a call that their revenue will accelerate on a larger base. It’s impossible for them to gain share at the rate they used to so the only answer is the entire industry must accelerate as well.

TSMC is probably one of the best management teams in the entire industry with the most credibility you can ask for. They are prudent, ROIC focused, conservative in their node shrinks yet aggressive in their capital spending. Simply put they do not miss. If they are investing in larger amounts for accelerating growth they believe will come, I am going to believe them.

This is the definition of long-term thinking and bold bets. They are pushing forward at an even faster pace at the peak of their dominance in order to ensure they continue to hold share. And everything is pointing to the diversity and strength of the entire semiconductor ecosystem, and I think that the answer is clear. The 2020s are going to be a better decade than the one before it for the entire semiconductor ecosystem.

Passing Price

I want to briefly mention the gross margin part of the equation. Every quarter there is a lot of hang wringing about the sustainability of the gross margin at TSMC. Last quarter analysts got really hung up on “51% or greater” long-term margins and asked in as many ways as possible if that margin was sustainable.

This quarter of course they put up 53% gross margin and now are guiding to “53% or greater” margin longer term. The bar of course has shifted higher. The right answer and framing around the gross margin sustainability debate are that TSMC really is one of the only games in town, and the demand for their capacity is intense. I mentioned briefly that TSMC can just pass price as much as they want in the Rising Tide of Semiconductor Costs and I think that will continue.

No matter how much capex spend is required and how much depreciation and amortization will grow as a part of TSMC’s cost, TSMC is simply not a price taker. They will raise prices and pass their costs onto their customers, and in this case, it seems like they are able to pass on more than just the cost they take. If they can maintain 53%+ margins against rising CoGs, this means that customers will be taking price raises on the chin. Because what other choice do they really have? Intel’s Foundry business is still more of an idea more than a meaningful business, and Samsung is growing but relatively small. TSMC will get the money that they are due.

There’s a lot more in the transcript itself, which I recommend reading if you have some time. TSMC continues to believe I think that the continued prepayments by their customers are another indication that the fabless companies get it as well. They want more capacity because their businesses are well but they are capacity constrained.

An interesting idea I had was that the capacity precommitments in order to secure capacity feels a bit like the ASML investment by INTC / TSMC. It’s clearly a greater good, there is really only one company that can achieve it, and it’s going to cost a lot of money. In order for the economics to work at TSMC will need a lot of money.

Fabricated Knowledge @_fabknowledge_

There is a real chance that we look back at the TSM capacity commitments from their customers akin to EUV commitments from INTC/TSM when ASML was struggling to ramp. A communal good that must be paid for in order to secure the future and paid by everyone.

Anyways that’s it for today. I just wanted to cover these points for now, and I’ll be posting a lot more content like this but for the ~100s of other semiconductor companies that will be reporting in the next month. I just always love to start with the biggest and baddest first.

From Fabricated Knowledge

Let’s learn more about the world’s most important manufactured product. Meaningful insight, timely analysis, and an occasional investment idea.

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Self-Aligned Via Process Development for Beyond the 3nm Node

Self-Aligned Via Process Development for Beyond the 3nm Node
by Tom Dillinger on 01-05-2022 at 6:00 am
Categories: Events, Foundries, TSMC
1 Comment

TEM DoD

The further scaling of interconnect and via lithography for advanced nodes is challenged by the requirement to provide a process window that supports post-patterning critical dimension variations and mask overlay tolerances.  At the recent international Electron Devices Meeting (IEDM) in San Francisco, TSMC presented a research update on their process development activities to realize a “self-aligned via” (SAV) for upcoming nodes, with an interconnect + via flow that provides improved manufacturability.[1]  This article summarizes the highlights of their presentation.

Introduction

The manufacturability of vias needs to address multiple litho, electrical, and reliability measures:

  • tolerance to overlay variation (aka, “edge placement error”, or EPE)
  • consistency of via resistance
  • robustness of via-to-adjacent metal dielectric properties
    • leakage current
    • maximum applied voltage before breakdown (Vbd)
    • dielectric reliability, measured as time-dependent dielectric breakdown (TDDB)

and, of course,

  • exceptional yield

(Note that these issues are most severe for the scaling of lower level metals and vias, denoted as “Mx” in the figures in this article.)

The overlay positioning between a via and an adjacent metal line impacts the dielectric breakdown – both Vbd and TDDB.  The figure below illustrates the overlay versus dielectric breakdown issue of a conventional via, for a representative EPE.

A “self-aligned” via (with a unique dielectric to an adjacent metal line) would provide greater process latitude to address the challenges listed above.

TSMC SAV Process

There are two key steps to the TSMC SAV process flow – the deposition of a “blocking layer” on metal lines and the selective deposition of dielectric-on-dielectric.

  • self-assembled monolayer (SAM) deposition on metal

A unique process chemistry step deposits a monolayer of a blocking material on an exposed metal surface.  This process is based on the affinity of organic chemical chains suspended in a solution to the metal.  The molecular chains are adsorbed on the metal surface, and self-assemble into an organized domain.  As the molecules adsorb over time, they will nucleate into groups and grow until the metal surface is covered with a monolayer.  (The monolayer packs tightly due to the van der Waals forces, the weak net attractive electric force between neutral organic solids.)

This SAM monolayer will serve as a blocking material.  Its composition needs to withstand the thermal exposure of the next step – the selective dielectric deposition on oxide.

  • selective dielectric-on-dielectric (DoD) deposition

Advanced nodes have leveraged atomic layer deposition (ALD) steps for several generations.  A gas phase “pre-cursor” is introduced into the process chamber.  Due to chemisorption, a unique pre-cursor monolayer is deposited on the wafer surface.  The pre-cursor adheres to the surface, but not to itself – no successive pre-cursor layers are deposited.  The chamber is then purged of the excess pre-cursor, and a co-reagent is subsequently introduced.  The chemical reaction results in a final monolayer of the desired reaction product that remains on the surface, while the excess co-reagent and reaction by-products are pumped out.  The cycle can be repeated to deposit multiple “atomic” layers.  ALD has been widely adopted for the deposition of metal and thin-oxide dielectric materials. A key advantage of current ALD processes is they operate uniformly and conformally on the exposed wafer surface.

An active area of research is to provide selective area atomic layer deposition, where the pre-cursor only adheres to a specific material surface.  The goal is the pre-cursor adsorption is suppressed on specific areas – in this case, the SAM molecules on the metal.

TSMC explored a selective deposition chemical process, for dielectric-on-dielectric layer buildup.  The images in the figure below depict the process flow to raise a dielectric layer above the existing surface oxide.

The SAM blocking layer precludes the selective deposition on the exposed dielectric.  As mentioned earlier, the blocking layer must withstand exposure to the elevated temperature of the dielectric-on-dielectric selective deposition.  TSMC indicated that higher DoD process temperatures improve the etch selectivity of the dielectric pedestal to the surrounding low-K inter-level dielectric for the via, to be discussed next.

The image labeled “DoD” in the figure above illustrates the wafer after dielectric-on-dielectric deposition and after removal of the SAM blocking material over the wafer, prior to the addition of the low-K dielectric.

The image on the right shows the final via connection, after low-K dielectric dep/etch and via patterning.  The added DoD material serves as a suitable “etch stop”, due to the lower etch rate compared to the low-K material.  This image illustrates the via-to-adjacent metal dielectric, in the presence of a significant overlay shift.

The figure below illustrates how the added dielectric-on-dielectric layer improves via robustness.  The “control” transmission electron microscopy image (without the DoD) shows excessive via etch of the original dielectric, with little isolation to the adjacent Mx line – not particularly tolerant of overlay error.  The DoD TEM image shows vastly improved isolation.

Experimental Electrical and Reliability Data for the SAV Process

The various figures below show the experimental data from the TSMC SAV process development team.  The Control data reflects the standard via patterning process without the selective DoD layer deposition.

  • via resistance

Both single via and via chain (yield assessment) resistance values show no difference between the control and DoD processes.

  • via-to-adjacent Mx reliability (leakage current, Vbd, TDDB)

To assess the process window, the TSMC team evaluated the leakage current and Vbd with an intentional via-to-Mx overlay shift.  Note that the control process would not support a 4nm overlay tolerance.

To ensure the additional DoD process steps did not adversely impact the characteristics of the existing Mx metal, TSMC shared evaluation data of metal lines with and without the DoD process.  The graphs below show there was no impact to metal line resistance or TDDB/electromigration reliability.

Summary

Continued interconnect scaling below the 3nm node will necessitate unique process development research to maintain electrical and reliability specs in the presence of (up to 4nm) overlay error.  The need for low-K interlevel dielectrics is a given – yet, the via etch in these materials is not especially tolerant of EPE.

TSMC has demonstrated a potential process flow for a “self-aligned via” with an additional DoD material.  The etch rate differential of the DoD results in more robust via-to-adjacent metal reliability.  This process flow utilizes two unique steps – the SAM of a blocking material on metal surfaces, and the selective ALD of a dielectric-on-dielectric.

Hopefully, selective ALD flows will transition soon from R&D to production fabrication – the potential impact of this chemistry for advanced node scaling is great.

-chipguy

References

[1]   Chen, H.-P., et al, “Fully Self-Aligned via Integration for Interconnect Scaling Beyond 3nm Node”, IEDM 2021, paper 22-1.

Note:  All images are copyright of the IEEE.

 

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Technology Design Co-Optimization for STT-MRAM

Technology Design Co-Optimization for STT-MRAM
by Tom Dillinger on 01-04-2022 at 6:00 am
Categories: Events, Foundries, TSMC
3 Comments

sense amplifier

Previous SemiWiki articles have described the evolution of embedded non-volatile memory (eNVM) IP from (charge-based) eFlash technology to alternative (resistive) bitcell devices.  (link, link)

The applications for eNVM are vast, and growing.  For example, microcontrollers (MCUs) integrate non-volatile memory for a variety of code and data storage tasks, from automotive control to financial bankcard security to IoT/wearable sensor data processing.  The key characteristics of eNVM are:

  • performance (read access time, write-verify cycle time)
  • data retention, over voltage and (especially) temperature extremes
    • bitcell “drift” over time (e.g., changes in device resistance leading to increasing bit-error rate)
  • write endurance (# of write cycles)
  • reliability (e.g., susceptibility to bit storage fails from external radiation or magnetic fields)
  • sensitivity to process variability
  • cost (e.g., # of additional mask lithography steps, compatibility of the embedded memory fabrication with existing FEOL and BEOL process steps)

(Note that the number of extra masks for embedded flash is large, and requires exposure to high programming voltage.)

  • yield (assume a double-error correction data width encoding will be used)

STT-MRAM

One of the leading eNVM technologies is the magnetic tunnel junction (MTJ) device, which uses a spin-torque transfer write current mechanism to toggle the MTJ between “parallel” (P) and “anti-parallel” (AP) states.  During a read cycle, the resistance differences between these states is sensed.

The figure below illustrates the process integration of STT-MRAM into a BEOL process for an advanced logic node. [1]

This STT-MRAM process offers a considerable cost advantage over scaling existing eFlash device technology.

In the image on the right above, the word lines run through the array connected to access devices.  During a read cycle, the column select line is grounded, and the resistance of the active MTJ determines the bitline current.  For a write cycle, since the MTJ programming current flows in opposite directions for a write to the AP state versus a write to the P state, the roles of the bitlines and column select lines are reversed, depending on the data value – i.e., write_1:  BL = 0V, CS = VPP;  write_0: BL = VPP, CS = 0V.

STT-MRAM technology does present some challenges, however.

  • small read sensing window

The read cycle needs to sense the difference in MTJ resistance between parallel and anti-parallel states.  Process variation in MTJ characteristics results in narrowing of this resistance contrast.  Sophisticated sense amplifier design methods are needed to compensate for a tight resistance margin.

  • strong MTJ sensitivity to temperature

The embedded MTJ IP will be subjected to temperature extremes both during assembly and during its operational lifetime.  The solder ball reflow and package-to-PCB attach process temperature is far higher than the maximum operational temperature, albeit only once and for a relatively short duration.  (Solder reflow temperatures are ~245C-260C.)  The operational environment for the demanding nature of MCU applications typically spans -40C to 125C.  The composition and diameter of the MTJ materials – i.e., the fixed and free magnetic layers, the tunneling oxide – are selected to maintain the spin-transfer torque properties throughout both assembly and operating temperature cycles.

Yet, due to the MTJ sensitivity to temperature, any attempt to pre-program data into the embedded STT-MRAM array prior to exposure to the assembly process temperatures would be fruitless.  Special technology-design co-optimization (TDCO) methods are needed to initialize (a portion of) the STT-MRAM array with key data measured at wafer test – more on these methods shortly.

Also, the read sensitivity – i.e., the resistance difference of P and AP states – is reduced at high temperature.  At cold temperature, the write current required to set the state of the bitcell is increased.  Again, TDCO techniques are required to compensate for these reduced margins at different temperature extremes.

  • process variation in MTJ characteristics

Sensing of the resistance differential also needs to address the process variation in MTJ devices, and the range of P and AP resistance states.

At the recent International Electron Devices Meeting (IEDM) conference in San Francisco, TSMC presented their TDCO approaches to address the STT-MRAM challenges above. [2] The rest of this article summarizes the highlights of their presentation, leading to the production release of STT-MRAM IP in their N22 ultra-low leakage process (N22ULL) node.

TSMC TDCO for N22ULL STT-MRAM

  • read sensing

When an address word line is raised along a set of bitcells in the MRAM array, current flows through the MTJ from the (pre-charged) bitline to the (grounded) select line.  The magnitude of the current on the bitline depends upon the P or AP state of the individual bitcell, and needs to be accurately sensed.  The MTJ process variation across the array suggests that each bitline sense circuit must be individually “trimmed” to match the specific local characteristics of the devices.  And, the strong temperature dependence of the MTJ needs to be dynamically compensated.

The optimized TSMC solution to MRAM bitline read sensing is illustrated below.

The read sense circuitry shown above is differential in nature, intended to amplify the voltage difference on lines Q and QB that evolves during the read cycle.  Prior to the start of the read, both nodes Q and QB are pre-charged.  When the address word line is raised, bitline current flows through the MTJ – in the figure above that is represented by current source Icell.

Note that the bitcells in the memory array are “single-ended” – i.e., there is only one connection to the sense amplifier.  (This is in contrast to a conventional 6T SRAM bitcell, for example, which provides connections to both Q and QB of the sense amplifier.)  As a result of the single connection, it is necessary to provide the QB line with a reference current, which needs to be between the Icell_P and Icell_AP values which may be flowing in the opposite side of the sense amplifier.  Further, this reference current needs to adapt to the local die temperature.

TSMC developed a unique design approach to provide the Iref value to a set of N bitcells + sense amplifiers on a word line in the array.

The figure above depicts N/2 reference MTJs that have been initialized to a P resistive state and N/2 reference MTJs in an AP state.  Their outputs have been dotted to provide a “merged” reference current.  The WL_REF signal is raised in a balanced timeframe as the active wordline – the resulting merged reference current is connected to the N sense amplifiers.  As a result, the Iref current to an individual SA is:

  ((N/2) * I_P) + ((N/2) * I_AP) / N = (I_P + I_AP) / 2

or the ideal “midpoint” current on the QB line.  After an appropriate duration into the read cycle, when a Q and QB voltage difference has been established, the Latch enable signal is raised to amplify the differential and drive Dout to the read value.

The approach to generate Iref for the sense amplifiers in an MRAM array bank provides both temperature compensation and some degree of “averaging” over process variation.

  • sense amplifier trimming

Nevertheless, MTJ process variation necessitates a per-sense amplifier correct design technique.  In the sense amplifier circuit figure above, devices N1A through N1X are in parallel with the sense pulldown transistor, all connected to Vclamp.  The switches in series with these devices represent the capability to trim the resistance of the Q line during a read cycle.  (The N2A through N2X devices provide a comparable, symmetric capability on the QB line, matching the loading on the Q line.)  During wafer-level testing, the memory BIST macro IP includes programming support to adjust the “trim code” to realize the lowest number of bit read failures during BIST, with error-correction circuitry disabled.  (This testing is performed at elevated temperature.)

  • OTP-MRAM

It was mentioned earlier that the elevated temperatures to which the MTJ is subjected during assembly preclude any attempt to write data into the array during die test.  Yet, the trim code values for each sense amplifier derived during memory BIST need to be retained in the array.  (Also, any built-in array self-repair BISR codes identified after BIST testing need to be stored.)

To address this issue, TSMC developed a unique approach, where some of the MTJ cells are subjected to a one-time programming (OTP) write sequence.  These cells retain their OTP values after exposure to the solder-reflow assembly temperature.

For these storage locations, a (tunnel oxide) “breakdown” voltage is applied to the MTJ to represent a stored ‘0’ value; the cell current will be high.  As illustrated above, any OTP junction that does not receive an applied breakdown voltage during programming will remain (P or AP) resistive, and thus will be sensed as storing a fixed ‘1’ value.

  • temperature-compensated write cycle

Whereas the sense amplifier (Rp versus Rap) read margin is reduced at high temperature, the MTJ write cycle is a greater challenge at low temps, where higher current are required to alter the MTJ state.  TSMC developed an operational write-verify cycle, where the applied write voltage is dynamically adapted to temperature.  The figure below shows a shmoo plot indicating the (wordline and bitline) write voltage sensitivity versus temperature (for AP-to-P and P-to-AP), and thus the need for compensation.

TSMC noted the “wakeup time” of the analog circuitry used to generate the corresponding write voltages adds minimally to the write cycle time.

Summary

At advanced process nodes, STT-MRAM IP offers an attractive evolution from eFlash for non-volatile storage – e.g., high retention, high durability, low additional process cost.  TSMC recently presented their TDCO approach toward addressing the challenges of this technology, adopting several unique features:

  • improved read sensing between Rp and Rap
    • derivation of read sense amplifier reference current compensated for temperature, with process variation averaging
    • per sense amplifier “trimming” for optimal read bit error rate
  • one-time programming cell storage prior to solder reflow assembly, to retain trim codes and array repair values
  • a temperature-compensated write voltage applied to the MTJ (as part of the write-verify cycle)

The characteristics and specs for the TSMC N22ULL STT-MRAM IP are appended below.

To quote TSMC, “Each emerging memory technology has its own unique advantages and challenges.  Design innovation is essential to overcome the new challenges and bring the memory IP to market.”

-chipguy

References

[1] Shih, Yi-Chun, et al., “A Reflow-capable, Embedded 8Mb STT-MRAM Macro with 9nS Read Access Time in 16nm FinFET Logic CMOS Process”, IEDM 20, paper 11.4.

[2] Chih, Yu-Der, et al., “Design Challenges and Solutions of Emerging Nonvolatile Memory for Embedded Applications”, IEDM 2021, paper 2.4.

Note:  All images are copyright of the IEEE.

 

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Advanced 2.5D/3D Packaging Roadmap

Advanced 2.5D/3D Packaging Roadmap
by Tom Dillinger on 01-03-2022 at 6:00 am
Categories: Events, Foundries, TSMC
1 Comment

SoIC futures

Frequent SemiWiki readers are no doubt familiar with the advances in packaging technology introduced over the past decade.  At the recent International Electron Devices Meeting (IEDM) in San Francisco, TSMC gave an insightful presentation sharing their vision for packaging roadmap goals and challenges, to address the growing demand for greater die integration, improved performance, and higher interconnect bandwidth.[1]  This article summarizes the highlights of the presentation.

Background

2.5D packaging

2.5D packages enable multiple die to be laterally positioned in close proximity, with signal redistribution interconnect layers (RDL) between the die fabricated on a silicon interposer present between the die and package substrate.  Through silicon vias (TSVs) provide the connectivity to the substrate.

The TSMC implementation of this technology is denoted as Chip-on-Wafer-on-Substrate (CoWoS), as was introduced a decade ago using multiple FPGA die in the package to expand the effective gate count.

The emergence of high bandwidth memory (HBM) stacked die as a constituent of the 2.5D integration offered system architects with new alternatives for the memory hierarchy and processor-to-memory bandwidth.

The development investment in 2.5D technology grew, now enabling the silicon interposer area to greatly exceed the “1X maximum” reticle size, to accommodate more (and more diverse) processing, memory and I/O die components (aka, “chiplets”).

Additional package fabrication steps incorporate local “trench capacitors” into the interposer.  Oxide-poly-oxide-poly material layers fill the trench, with the poly connected to the RDL supply metal.  The resulting decoupling capacitance reduces power supply droop considerably.

Alternative technologies have also been developed, replacing the full area silicon interposer with a local “silicon bridge” (CoWoS-L) between adjacent die embedded in an organic interposer, thus reducing cost (albeit with relaxed RDL interconnect dimensions).

Concurrently, for very low cost applications, the demand for higher I/O count die than could be supported with the conventional wafer-level chip-scale package (WLCSP) led to the development of a novel technology that expands the die surface area with a “reconstituted wafer”, on which the redistribution to a larger number of I/O bumps could be fabricated.

This Integrated FanOut (InFO) technology was originally developed for single die (as a WLCSP-like offering).  Yet, the application of this technique is readily extended to support the 2.5D integration of multiple heterogeneous die placed adjacent, prior to the reconstitution step. (The InFO_oS technology will be discussed shortly.)

3D die stacking

3D die stacking technology has also evolved rapidly.  As mentioned above, the fabrication of TSVs spanning between layers of DRAM memory die with “microbumps” attached at the other end of the TSV has enabled impressive levels of vertical stacking – e.g., eight memory die plus a base logic controller die in an HBM2e configuration.

Similarly, through-InFO vias (located outside the base die in the reconstituted wafer material) has enabled additional micro-bumped die to be vertically stacked above the base InFO die – e.g., a memory die on top of a logic die.

The most recent advancement in 3D stacking technology has been to employ bump-less “direct bonding” between two die surfaces.  Applying a unique thermal + compression process, two die surfaces are joined.  The metal pad areas on the different die expand to form an electrical connection, while the abutting dielectric surfaces on the two die are bonded.  Both face-to-face (F2F) and face-to-back (F2B) die orientations are supported.  The planarity and uniformity (warpage) requirements of the surfaces are demanding; particulates present on the surface are especially problematic.  TSMC denotes their 3D package technology as System-on-Integrated Chips, or “SoIC”.

As product architects are exploring the opportunities available with these packaging technologies, there is growing interest in combining “front-end” 3D stacked SoIC configurations with 2.5D “back-end” (InFO or CoWoS) RDL patterning and assembly.  The collective brand that TSMC has given to their entire suite of advanced packaging offerings is “3D Fabric”, as illustrated below.

TSMC 3D Fabric Roadmap

At IEDM, TSMC shared their strategy for improving performance, power efficiency, signal bandwidth, and heat dissipation for these technologies.  (The majority of the focus was on bonding technology for SoIC.)

CoWoS (2.5D)

    • increase package dimensions to 3X maximum reticle size for the Si interposer
    • expectation is that stacked SoIC die will be integrated with multiple HBM stacks

InFO_oS (2.5D)

The original InFO offering was as an evolution to WLCSP, first as a single die, and then as a base die with another added on top connected to the through-InFO vias.  TSMC is also expanding the InFO offering to support multiple adjacent die embedded in the reconstituted wafer; the RDL layers are then fabricated and microbumps added for attach to a substrate (InFO-on-Substrate, of InFO_oS).  A projection for the InFO_oS configurations to be supported is illustrated below.

SoIC (3D)

The roadmap for 3D package development is shown below, followed by a table illustrating the key technical focus – i.e., scaling the bond pitch of the (F2F or F2B) stacked connections.

The bond pitch (and other metrics) for microbump technology evolution are included with the SoIC direct bonding measures in the table above for comparison.

As shown in the table above, TSMC has defined a new (relative comparison) metric to represent the roadmap for 3D stack bonding technology – an “Energy Efficiency Performance” (EEP) calculation.  Note that the target gains in EEP are driven by the aggressive targets for scaling of the bond pitch.

EEP = (bond_density) * (performance) * (energy efficiency)

Much like the IC scaling associated with Moore’s Law, there are tradeoffs in 3D bond scaling for performance versus interconnect density.  And, like Moore’s Law, the TSMC roadmap goals are striving for a 2X improvement in EEP for each generation.

SoIC Futures

As an illustration of the future potential for 3D stacking, TSMC provided an example of a three-high stacked structure, as shown below.

Note that the assumption is that future HBM stacks will migrate from a microbump attach technology within the stack to a bonded connection – the benefits of this transition on performance, power, and thermal resistance (TR) are also shown in the figure.

heat dissipation

Speaking of thermal resistance, TSMC emphasized the importance of both the bonding process for low TR and design analysis of the proposed 3D stack configuration, to ensure the junction temperature (Tj) across all die remains within limits.

The IEDM presentation referred to additional research underway at TSMC to evaluate liquid-cooling technology options. [2] As illustrated below, “micro-pillars” can be etched into a silicon lid bonded to the assembly, or even directly into the die, for water cooling.

Summary

Advanced 2.5D and 3D packaging technologies will provide unique opportunities for systems designers to optimize performance, power, form factor (area and volume), thermal dissipation, and cost.  TSMC shared their development roadmap for both 2.5D and 3D configurations.

The 2.5D focus will remain on support of larger substrate sizes for more (heterogeneous) die integration;  for markets focus on cost versus performance, different interposer/bridge (CoWoS) and reconstituted wafer (InFO technology options are available.

3D stacking technology will receive the greatest development focus, with an emphasis on scaling the interface bond pitch.  The resulting “2X improvement in EEP” for each SoIC generation is the target for the new “More than Moore” semiconductor roadmap.

-chipguy

References

[1] Yu, Douglas C.H., et al, “Foundry Perspectives on 2.5D/3D Integration and Roadmap”, IEDM 2021, paper 3-7.

[2]  Hung, Jeng-Nan, et al., “Advanced System Integration for High Performance Computing with Liquid Cooling”, 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), p. 105-111.

Note:  All images are copyright of the IEEE.