Posted on

TSMC Doubles Down on Semiconductor Packaging!

TSMC Doubles Down on Semiconductor Packaging!
by Daniel Nenni on 06-14-2023 at 6:00 am
Categories: Chiplet, Foundries, TSMC
4 Comments

TSMC 3DFabric Integration

Last week TSMC announced the opening of an advanced backend fab for the expansion of the TSMC 3DFabric System Integration Technology. It’s a significant announcement as the chip packaging arms race with Intel and Samsung is heating up.

Fab 6 is TSMC’s first all-in-one advanced packaging and testing fab which is part of the increasing investment in packaging TSMC is making. The fab is ready for mass production of the TSMC SoIC packing technology. Remember, when TSMC says mass production they are talking about Apple iPhone sized mass production, not engineering samples or internal products.

Today packaging is an important part of a semiconductor foundry offering. Not only is it a chip level product differentiator, it will take foundry customer loyalty to a whole new level. This will be critical as the chiplet revolution takes hold making it much easier for customers to be foundry independent. Chiplet packaging however is very complex and will be foundry specific which is why TSMC, Intel, and Samsung are spending so much CAPEX to secure their place in the packaging business.

The TSMC 3DFabric is a comprehensive family of 3D Silicon Stacking and Advanced Packaging Technologies:

  • TSMC 3DFabric consists of a variety of advanced 3D Silicon Stacking and advanced packaging technologies to support a wide range of next-generation products:
    • On the 3D Si stacking portion, TSMC is adding a micro bump-based SoIC-P in the TSMC-SoIC®family to support more cost-sensitive applications.
    • The 2.5D CoWoS®platform enables the integration of advanced logic and high bandwidth memory for HPC applications, such as AI, machine learning, and data centers. InFO PoP and InFO-3D support mobile applications and InFO-2.5D supports HPC chiplet integration.
    • SoIC stacked chips can be integrated in InFO or CoWoS packages for ultimate system integration.
  • CoWoS Family
    • Aimed primarily for HPC applications that need to integrate advanced logic and HBM.
    • TSMC has supported more than 140CoWoS products from more than 25
    • All CoWoS solutions are growing in interposer size so they can integrate more advanced silicon chips and HBM stacks to meet higher performance requirements.
    • TSMC is developing a CoWoS solution with up to 6Xreticle-size (~5,000mm2) RDL interposer, capable of accommodating 12 stacks of HBM memory.
  • InFO Technology
    • For mobile applications, InFO PoP has been in volume production for high-end mobile since 2016 and can house larger and thicker SoC chips in smaller package form factor.
    • For HPC applications, the substrateless InFO_M supports up to 500 square mm chiplet integration for form factor-sensitive applications.
  • 3D Silicon stacking technologies
    • SoIC-P is based on 18-25μm pitch μbump stacking and is targeted for more cost-sensitive applications, like mobile, IoT, client, etc.
    • SoIC-X is based on bumpless stacking and is aimed primarily at HPC applications. Its chip-on-wafer stacking schemes feature 4.5 to 9μm bond pitch and has been in volume production on TSMC’s N7 technology for HPC applications.
    • SoIC stacked chips can be further integrated into CoWoS, InFo, or conventional flip chip packaging for customers’ final products.

“Chiplet stacking is a key technology for improving chip performance and cost-effectiveness. In response to the strong market demand for 3D IC, TSMC has completed early deployment of advanced packaging and silicon stacking technology production capacity, and offers technology leadership through the 3DFabricTM platform,” said Dr. Jun He Vice President, Operations / Advanced Packaging Technology & Service, and Quality & Reliability. “With the production capacity that meets our customers’ needs, we will unleash innovation together and become an important partner that customers trust in the long term.”

TSMC’s customer centric culture will be a big part of the chiplet packaging revolution. By working with hundreds of customers you can bet TSMC will have the most comprehensive IC packaging solutions available for fabless and systems companies around the world, absolutely.

TSMC Press Release:
TSMC Announces the Opening of Advanced Backend Fab 6, Marking a Milestone in the Expansion of 3DFabric™ System Integration Technology

Also Read:

TSMC Clarified CAPEX and Revenue for 2023!

TSMC 2023 North America Technology Symposium Overview Part 1

TSMC 2023 North America Technology Symposium Overview Part 2

TSMC 2023 North America Technology Symposium Overview Part 3

TSMC 2023 North America Technology Symposium Overview Part 4

TSMC 2023 North America Technology Symposium Overview Part 5

Posted on

TSMC Clarified CAPEX and Revenue for 2023!

TSMC Clarified CAPEX and Revenue for 2023!
by Daniel Nenni on 06-06-2023 at 2:00 pm
Categories: Events, Foundries, TSMC
4 Comments

TSMC HQ Taiwan

TSMC clarified CAPEX and revenue for 2023 last night at the Annual Shareholders Meeting. Last year TSMC guided up during this meeting but this year they guided down. CAPEX was guided down to the lower end of $36B-$32B.  Revenue was guided down from low-single to mid-single digit so maybe down another percent or two. The TSMC Jan – May 2023 revenue report indicates a decrease of 1.9 percent compared to the same period in 2022 so I think TSMC is being very conservative here.

Other foundries may not be as fortunate. Globalfoundries is already -5% in Q1 and UMC is -17% Jan-May 2023. In contrast TSMC started the year strong with +16% in January and +11% in February. Things turned bad in March with -15% and April -14%. At the TSMC Symposium CC Wei joked about his horrible forecasting but coming off the strongest year in the history of TSMC it was not a surprise.

“The year 2022 was a landmark year for TSMC. Supported by our strong technology leadership and differentiation, we delivered a thirteenth-consecutive year of record revenue, with strong profitable growth. Our 2022 annual revenue increased 33.5% year-over-year in U.S. dollar terms, while our EPS rose to NT$39.20, nearly tripling over the past three years.”

A landmark year indeed. TSMC manufactured 12,698 products for 532 customers in 2022. Hopefully we can all recognize this incredible achievement. Unfortunately, 2023 will also be a landmark year for a YoY decline and the pandemic is still to blame.

TSMC predicts that the second half of 2023 will improve so we may be at the bottom. 2024 also looks very promising but of course it is too soon to tell. According to the  World Semiconductor Trade Statistics, the global semiconductor industry is forecasted to grow 11.8% to $576B in 2024 with a major rebound expected in the memory segment, a surge of about 40% from last year.

The other news from the meeting echoed the Symposium which is good news:

 “In Taiwan, our N3 has just entered volume production in Tainan Science Park. We are also preparing for N2 volume production starting in 2025, which will be located in Hsinchu and Taichung Science Parks. In the U.S., we are in the process of building two advanced semiconductor fabs in Arizona, with N4 and N3 process technology, respectively. We are also building a 12-inch specialty technology fab in Kumamoto, Japan.”

TSMC was crystal clear in the reasoning for building fabs around the world. TSMC’s business model has always been customer centric and customers want fabs near their customers. This customer demand is not just for semiconductor manufacturing, other manufacturing is localizing as well, and again it is a direct result of the pandemic which broke supply chains around the world.

“N2 technology development is on track, with risk production scheduled in 2024 and volume production in 2025. Our 2-nanometer technology will be the most advanced semiconductor technology in the industry in both density and energy efficiency when it is introduced.”

Interesting wording here and I do agree N2 will be denser and more power efficient than Intel 20A or Samsung 3nm. I would also add more cost effective as no one in the foundry business has the economies of scale to match TSMC.

One thing you have to remember is that when TSMC says volume N2 production in 2025 that means Apple which is a multi-billion transistor SoC shipped by the millions. TSMC is not talking about internal product, engineering samples or chiplets. The mainstream media misses this point every time. Either they are ignorant or they are intentionally besmirching TSMC to get clicks. Either way it is unethical, my opinion.

“To help customers unleash their product innovations with fast time-to-market, TSMC provides customers with comprehensive infrastructure needed to optimize design productivity and cycle times. TSMC continues to expand our Open Innovation Platform® (OIP), providing over 55,000 items of libraries and silicon IP portfolio, more than 43,000 technology files, and over 2,900 process design kits, from 0.5-micron to 3-nanometer in 2022.”

As most people know I have been part of this ecosystem since it started so I know it better than most. The one thing that I would add here is that with the overwhelming success of TSMC N3, the ecosystem has never been stronger for TSMC so there is significant momentum for the N2 transition, absolutely.

Also Read:

TSMC 2023 North America Technology Symposium Overview Part 1

TSMC 2023 North America Technology Symposium Overview Part 2

TSMC 2023 North America Technology Symposium Overview Part 3

TSMC 2023 North America Technology Symposium Overview Part 4

TSMC 2023 North America Technology Symposium Overview Part 5

Posted on

Investing in a sustainable semiconductor future: Materials Matter

Investing in a sustainable semiconductor future: Materials Matter
by Daniel Nenni on 05-31-2023 at 6:00 am
Categories: EMD Electronics, Foundries, Semiconductor Services, TSMC

EMD LinkedIn Twitter Materials Matter

In 2020 TSMC established its Net Zero Project with a goal of net zero emissions by 2050. I remember wondering how could this possibly be done before 2050 or at all for that matter. After working with TSMC for 20+ years I have learned never to bet against them on any topic and green manufacturing is one of them, absolutely.

TSMC presented on green manufacturing at the recent symposium in Silicon Valley. Clearly energy and water resources are critical parts of any net zero project but carbon emissions are also a of great importance and that means materials. In regards to semiconductor manufacturing materials we have experts here on SemiWiki.

EMD Electronics has a presence in 66 countries and over 100 years of invaluable experience in the electronic materials space delivering a broad portfolio of semiconductor and display materials for cutting-edge electronics.

EMD Electronics recently published a paper: INVESTING IN A SUSTAINABLE SEMICONDUCTOR FUTURE – MATERIALS MATTER.

It is a very interesting comprehensive look at innovative sustainable semiconductor materials techniques that decrease carbon emissions, improve resource efficiency and productivity, and highly contribute to achieving net zero semiconductor.

“It is amazing where collaboration can take us. Sustainability is no longer the result of individuals; only by working together can we get closer to our goals for a sustainable future! Brita Grundke, Head of Sustainability, EMD Electronics”

Here is the introduction. This paper is freely available and well worth the read for semiconductor professionals at all levels:

Emissions from semiconductor manufacturing are a growing segment of global greenhouse gas (GHG) emissions. There are two reasons behind this trend. First, the demand for semiconductor chips is growing. Our technology appears in everything from mobile phones to automobiles, where the number of chips per vehicle increases every year. Data storage, which relies on the semiconductor industry, is exploding. Second, today’s manufacturing processes have more deposition and etch steps than ever. Each step consumes water and electricity and creates GHG emissions.

Semiconductor companies large and small talk about achieving climate neutrality by 2030. That sounds like a great goal. But merely achieving that goal won’t solve the emissions problem. How we get there matters.

Buying carbon offsets is an easy way out. It isn’t the best long-term answer, because many offsets are not as effective as they claim to be. Some may even make the problem worse, defeating the purpose [1]. And relying on offsets can make internal actions seem less pressing. It is best to see offsets as a temporary or last-choice option.

Semiconductor industry leaders are, of course, doing more than buying offsets. They are investing in renewable energy, improving the energy efficiency of their processes, and finding ways to reduce waste. These actions are helpful, and we must do more. Despite modest success in reducing emissions per wafer or per revenue, demand for semiconductor chips is growing faster than the improvements can handle. We need more drastic reductions, and that starts by examining the sources.

Bottom Line: Climate change is real and semiconductor manufacturing is under a microscope now that it is being regionalized due to the shortages and supply chain issues we suffered during the pandemic. If you really want to know why semiconductor manufacturing left the US it was due to the Environmental protection Agency crack down on water, ground, and air pollution. I grew up in Silicon Valley so I had front row seat to the environmental issues of semiconductor manufacturing. Now that semiconductor manufacturing is coming back to the US and other parts of the world sustainability is front and center once again.

Also Read:

Step into the Future with New Area-Selective Processing Solutions for FSAV

Integrating Materials Solutions with Alex Yoon of Intermolecular

Ferroelectric Hafnia-based Materials for Neuromorphic ICs

Posted on

Chiplet Interconnect Challenges and Standards

Chiplet Interconnect Challenges and Standards
by Daniel Payne on 05-25-2023 at 10:00 am
Categories: Chiplet, EDA, Synopsys, TSMC

Multi die IP min

For decades now I’ve watched the incredible growth of SoCs in terms of die size, transistor count, frequency and complexity. Instead of placing all of the system complexity into a single, monolithic chip, there are now compelling reasons to use a multi-chip approach, like when the maximum die size limit is reached, or it’s more cost effective to use two or more smaller chiplets designed in a variety of technology nodes. Taking the multi-die system path introduces new chiplet interconnect challenges:

  • Reliable connectivity
  • High bandwidth
  • Low power
  • Low latency
  • Standards support

Fortunately for the industry there’s been a collective effort to develop standards, and the Universal Chiplet Interconnect Express™ (UCIe™) has gained traction by enabling package-level integration through a die-to-die interconnect along with a connectivity protocol, so that multiple vendors can grow an ecosystem through interoperability. UCIe covers three stack layers, and the PHY layer defines the electrical interface.

Synopsys has been delivering IP for many years now across many domains, like: Interface, Foundation, Processor, Security, Analog, Subsystems. They’ve also joined the UCIe Consortium, contributing to the specification of the standard. There’s a UCIe PHY IP from Synopsys, along with a UCIe Controller IP and verification IP.

Synopsys Multi-die IP

In March 2023 Synopsys announced that their UCIe PHY IP had a tape-out on the TSMC N3E process node.

For reliable connectivity the UCIe standard has up to 8 spare pins per direction, allowing repair of the functional links.

Link Repairs

Variations in the die-to-die interface signals are monitored by Signal Integrity Monitors (SIM), then the Monitoring, Test and Repair controller can determine the health of the multi-die system for predictive maintenance of the links. Synopsys has the Silicon Lifecycle Management tools to monitor the UCIe interface while its operating, detecting soft or hard errors.

Synopsys Monitoring, Test and Repair (MTR) controller

Bandwidth for UCIe using the Synopsys PHY IP is up to 5Tbps/mm efficiency. The Controller IP supports streaming protocols as well as PCI Express and CXL protocols, delivering secure, low-latency data.

Coming up to speed on the UCIe specification takes precious engineering time, so re-using protocol verification IP is going to save your team valuable time to market. Verification IP running on a software simulator provides a good start, then adding hardware emulation with Synopsys ZeBu and prototyping with Synopsys HAPS Platform offer more time savings to debug the whole system running software.

Routing the UCIe signals between dies is automated by the Synopsys 3DIC Compiler tool, and it works for 2.5D chiplets.

Summary

Systems engineers today still have to decide between two approaches for implementation, the traditional single-chip SoC, or the multi-die system. EDA vendors like Synopsys have long been automating the EDA tasks for a single-chip SoC, and they’ve also extended their automation into the realm of 2.5D by developing new EDA tools, verification and IP for multi-die systems.

The interconnect challenges of multi-die systems have been addressed through standardization efforts like UCIe, which lowers the risks for new projects considering chiplet-based systems. Synopsys is one of the few EDA and IP vendors with such broad support of multi-die systems.

Related Blogs

Posted on

Alphawave Semi Showcases 3nm Connectivity Solutions and Chiplet-Enabled Platforms for High Performance Data Center Applications

Alphawave Semi Showcases 3nm Connectivity Solutions and Chiplet-Enabled Platforms for High Performance Data Center Applications
by Daniel Nenni on 05-04-2023 at 6:00 am
Categories: 5G, AI, Alphawave Semi, Chiplet, Events, IP, TSMC

Alphawave Semi 3nm Eye Diagram

There were quite a few announcements at the TSMC Technical Symposium last week but the most important, in my opinion, were based on TSMC N3 tape-outs. Not only is N3 the leading 3nm process it is the only one in mass production which is why all of the top tier semiconductor companies are using it. TSMC N3 will be the most successful node in the history of the TSMC FinFET family, absolutely.

(Graphic: TSMC)

In order to tape-out to 3nm you need IP and high speed SerDes IP is critical for HPC applications such as AI which is now the big semiconductor driver for leading edge silicon. Enabling chiplets at 3nm is also a big deal and that is the focus of this well worded announcement:

Successful launch of 3nm connectivity silicon brings chiplet-enabled custom silicon platforms to the forefront Alphawave Semi 3nm Eye Diagram

(Graphic: Business Wire)

LONDON, United Kingdom, and TORONTO, Canada – April 25, 2023 – Alphawave Semi (LSE: AWE), a global leader in high-speed connectivity for the world’s technology infrastructure, today announced the bring-up of its first connectivity silicon platform on TSMC’s most advanced 3nm process with its ZeusCORE Extra-Long-Reach (XLR) 1-112Gbps NRZ/PAM4 serialiser-deserialiser (“SerDes”) IP.

An industry-first live demo of Alphawave Semi’s silicon platform with 112G Ethernet and PCIe 6.0 IP on TSMC 3nm process will be unveiled at the TSMC North America Symposium in Santa Clara, CA on April 26, 2023.

The 3nm process platform is crucial for the development of a new generation of advanced chips needed to cope with the exponential growth in AI generated data, and enables higher performance, enhanced memory and I/O bandwidth, and reduced power consumption. ZeusCORE XLR Multi-Standard-Serdes (MSS) IP is the highest performance SerDes in the Alphawave Semi product portfolio and on the 3nm process will pave the way for the development of future high performance AI systems. It is a highly configurable IP that supports all leading edge NRZ and PAM4 data center standards from 1112 Gbps, supporting diverse protocols such as PCIe Gen1 to Gen6 and 1G/10G/25G/50G/100 Gbps Ethernet.

This flexible and customizable connectivity IP solution together with Alphawave Semi’s chiplet-enabled custom silicon platform which includes IO, memory and compute chiplets, allows end-users to produce high performance silicon specifically tailored to their applications. Customers can benefit from Alphawave Semi’s application optimized IP-subsystems and advanced 2.5D/3D packaging expertise to integrate advanced interfaces such Compute Express Link (CXLTM), Universal Chiplet Interconnect ExpressTM (UCIeTM), High Bandwidth Memory (HBMx), and Low-Power Double Data Rate DRAM (LP/DDRx/) onto custom chips and chiplets.

“We are thrilled to be one of the first companies to successfully demonstrate our highest performance silicon platform with our XLR 112G Ethernet and PCIE6.0 SerDes IP on TSMC’s most advanced 3nm technology”, said Tony Pialis, CEO and co-founder of Alphawave Semi. “This represents a significant stepforward in our execution of Alphawave Semi’s strategy to be a vertically-integrated semiconductor leader in high-speed connectivity. Thanks to our rapidly growing partnership with TSMC through the Open Innovation Platform© (OIP), we continue to deliver innovative, high-performance custom silicon and IP solutions to our customers in data center, compute, networking, AI, 5G, autonomous vehicles, and storage applications.”

“Alphawave Semi continues to see growing demand from our hyperscaler customers for purpose-built silicon with very high-speed connectivity interfaces, fueled by an exponential increase in processing of AI-generated data”, said Mohit Gupta, SVP and GM, Custom Silicon and IP, Alphawave Semi. “We’re engaging our leading customers on chiplet-enabled 3nm custom silicon platforms which include IO, memory, and compute chiplets. Our Virtual Channel Aggregator (VCA) partnership with TSMC has provided invaluable support, and we look forward to accelerating our customers’ high-performance designs on TSMC’s 3nm process.”

About Alphawave Semi

Alphawave Semi is a global leader in high-speed connectivity for the world’s technology infrastructure. Faced with the exponential growth of data, Alphawave Semi’s technology services a critical need: enabling data to travel faster, more reliably and with higher performance at lower power. We are a vertically integrated semiconductor company, and our IP, custom silicon, and connectivity products are deployed by global tier-one customers in data centers, compute, networking, AI, 5G, autonomous vehicles, and storage. Founded in 2017 by an expert technical team with a proven track record in licensing semiconductor IP, our mission is to accelerate the critical data infrastructure at the heart of our digital world. To find out more about Alphawave Semi, visit: awavesemi.com.

Also Read:

TSMC 2023 North America Technology Symposium Overview Part 1

Alphawave Semi at the Chiplet Summit

Alphawave IP is now Alphawave Semi for a very good reason!

High-End Interconnect IP Forecast 2022 to 2026

 

Posted on

TSMC 2023 North America Technology Symposium Overview Part 5

TSMC 2023 North America Technology Symposium Overview Part 5
by Daniel Nenni on 04-27-2023 at 10:00 am
Categories: Events, Foundries, TSMC

Global Footprint

TSMC also covered manufacturing excellence. The TSMC “Trusted Foundry” tagline has many aspects to it, but manufacturing is a critical one. TSMC is the foundry capacity leader but there is a lot more to manufacturing as you will read here. Which brings us to the manufacturing accomplishments from the briefing:

To meet customers’ growing demand, TSMC has accelerated its fab expansion rate:
  • From 2017 to 2019, TSMC built around 2 phases of fabs on average per year.
  • From 2020 to 2023, the average will significantly increase to around 5
  • In the past two years, TSMC started the construction of 10 new phases in total, including 5 phases of wafer fabs in Taiwan, 2 phases of advanced packaging fabs in Taiwan, and 3 phases of wafer fabs overseas.
    • The overseas capacity of 28nm technology and below will be 3X larger in 2024 than it was in 2020.
    • In Taiwan, phases 5, 6, and 8 of Fab 18 in Tainan are the base of TSMC’s N3 volume production. In addition, TSMC is preparing new fabs, Fab 20 in Hsinchu and a new site in Taichung, for N2 production.
    • In the US, TSMC is planning for 2 fabs in Arizona.
  • The first fab for N4 has started tools move-in, and volume production will be in 2024.
  • The second fab is under construction now and is planned for N3 production.
  • Combined capacity for both fabs will reach 600K wafers per year.
    • In Japan, TSMC is building a fab in Kumamoto to provide foundry services for 16/12nm and 28nm family technologies to address strong global market demand for specialty technologies. Construction of this fab has begun and volume production will be in 2024.
    • In China, a new phase for 28nm technology started volume production in 2022.

TSMC’s leadership on advanced technology defect density (D0) and defective parts per million (DPPM) has demonstrated its manufacturing excellence.

    • The process complexity of N5 is much higher than N7, but N5’s yield improvement is even better than N7 at the same stage.
    • TSMC’s N3 technology has demonstrated industry-leading yield in high-volume production, and its D0 performance is already on par with N5 at the same stage.
      • TSMC’s N7 and N5 technologies have demonstrated industry-leading DPPM, including smartphones, computers, and cars, and TSMC is confident that N3 DPPM will catch up with N5 very soon.
3DFabric™ Manufacturing
  • By leveraging TSMC’s industry-leading 3DFabric™ manufacturing, customers can overcome the challenges of system-level design complexity and speed up product innovation.
  • CoWoS and InFO families have reached fairly high-level yields very soon after their volume productions.
  • The integrated yield of SoIC and advanced packaging will achieve the same level as the CoWoS and InFO families.
Green Manufacturing
    • To achieve the goal of net zero emissions by 2050, TSMC continues to evaluate and invest in all types of opportunities to reduce greenhouse gas emissions.
    • In 2022, TSMC’s direct greenhouse gas emissions have significantly dropped to 32% from 2010 levels.
    • This was achieved through reducing process gas consumption, replacing global warming potential gases, installing on-site abatement systems, and improving gas removal efficiency.

TSMC aims to double production energy efficiency for every process node after five years of volume production.

    • For N7 technology, the energy efficiency improved by 5X in the fifth year of its volume production.
    • For N5 technology, TSMC expects to see energy efficiency improvement by 5X by 2024.
    • TSMC has built an innovative chiller system with AI capabilities, which significantly contributed to improving cooling energy efficiency.

Last year, TSMC’s first water reclamation plant in southern Taiwan started supplying 5,000 metric tons of water per day. Today, it’s 20,000 tons per day.

    • By 2030, TSMC’s tap water consumption per unit of production will be reduced to 60% of 2020 level.
    • At TSMC Arizona, TSMC plans to build an industrial water reclamation plant to help the company reach near-zero liquid discharge. When completed, TSMC Arizona will be the greenest semiconductor manufacturing facility in the U.S.

After attending a handful of conferences in 2023 I must say that the TSMC Technical Symposium was by far the best. I don’t know the final attendance numbers but more than 1,600 people registered to attend this event. The exhibit hall was very busy and well stocked with food. Quite a few of the companies we work with on SemiWiki were exhibiting and I was told that for the cost it had by far the best ROI of semiconductor conferences.

The TSMC Technical Symposium will next go to Austin, Boston, Taiwan, Europe, Israel, China, and Japan. TSMC certainly knows how to build an ecosystem of customers, partners, and suppliers, absolutely.

Also Read:

TSMC 2023 North America Technology Symposium Overview Part 1

TSMC 2023 North America Technology Symposium Overview Part 2

TSMC 2023 North America Technology Symposium Overview Part 3

TSMC 2023 North America Technology Symposium Overview Part 4

Posted on

TSMC 2023 North America Technology Symposium Overview Part 4

TSMC 2023 North America Technology Symposium Overview Part 4
by Daniel Nenni on 04-27-2023 at 8:00 am
Categories: Automotive, Chiplet, Events, Foundries, TSMC
1 Comment

TSMC Specialty Technology 2023

TSMC covered their specialty technologies in great detail. Specialty is what we inside the ecosystem used to call weird stuff meaning non-mainstream and fairly difficult to do on leading edge processes.  Specialty technologies will play an even more important part of semiconductor design with the advent of chiplets where die from specialty processes can be integrated with mainstream process die.

Specialty processes also fill fabs. As you can see TSMC is pushing heavily on N6RF to fill the N7 fabs. Here is the lengthy list of specialty accomplishments from the media kit:

TSMC offers the industry’s most comprehensive specialty technology portfolio, covering Power Management, RF, CMOS image sensing, and much more for a broad range of applications:

  • Automotive
    • As the automotive industry moves toward autonomous driving, compute requirement is increasing at a very fast rate and needs the most advanced logic technology. By 2030, TSMC expects that 90% of all cars will have ADAS function, with L1, L2, and L2+/L3 each taking up 30% of that market.
    • In the past three years, TSMC rolled out ADEP (Automotive Design Enablement Platform) by offering industry-leading Grade-1 qualified N7A and N5A to unleash customers’ automotive innovation.
    • To give customers a head start on automotive product design before technology is auto-ready, TSMC introduced Auto Early as a steppingstone to enable an early design start and shorten product time-to-market.
      • N4AE, based on N4P, enables customers to start risk production in 2024.
      • N3AE serves as a steppingstone to N3A, which will be fully automotive qualified in 2025.
      • N3A, once qualified and released, will be the world’s most advanced automotive logic technology.
  • Advanced RF Technologies for 5G & Connectivity
    • In 2021, TSMC released N6RF with best-in-class transistor performance, including speed and power efficiency, based on our record-setting 7nm logic technology.
    • Combining the superb RF performance and excellent 7nm logic speed and power efficiency, TSMC’s customers can enjoy 49% power reduction from an RF SoC chip with half digital and half analog thru migration from 16FFC to N6RF releasing the power budget of mobile devices to support other growing features.
    • Today, TSMC announced the most advanced RF CMOS technology, N4PRF, that will be released in the second half of 2023.
      • Offers 77X logic density increase and 45% logic power reduction under the same performance moving from N6RF.
      • 32% MOM cap density increase in N4PRF is offered when compared with its predecessor, N6RF.
  • Ultra-Low Power
    • TSMC’s ultra-low power solutions continue to drive Vdd reduction to push power saving, which is essential to electronics.
    • With continued technology enhancement to lower minimum Vdd from 0.9V at 55ULP to less than 0.4V in N6e, TSMC offers a wide range of voltage operation to enable dynamic voltage scaling design for optimal power/performance.
    • TSMC’s coming N6e solution can provide around 9X logic density with >70% power reduction vs. the N22 solution, an attractive solution for wearables.
  • MCU / Embedded Nonvolatile Memories
    • TSMC’s most advanced eNVM technology has progressed to 16/12nm FinFET-based technology, which allows customers to leverage superb performance in compute from FinFET transistors.
    • Due to the growing complexity of traditional floating gate-based eNVM or ESF3, TSMC has also heavily invested in new embedded memory technologies, such as RRAM and MRAM.
    • Both new technologies have now come to fruition, going into production at 22nm & 40nm nodes.
    • TSMC is planning for 6nm development
  • RAM: Moved into 40/28/22RRAM production during the first quarter of 2022
    • TSMC’s 28RRAM is also progressing well, with reliable performance that is automotive capable.
    • TSMC is now developing the next generation 12RRAM, which is expected to be ready by the first quarter of 2024.
  • MRAM: 22MRAM started production in 2020 for IoT applications. Now TSMC is working with customers to bring MRAM technology to future automotive applications and expects to qualify for automotive Grade 1 in the second quarter of 2023.
  • CMOS Image Sensing
    • While the smartphone camera has been the main driving force of CMOS image sensing technology, TSMC expects that automotive cameras will drive the next wave of CIS growth.
    • To serve the future sensor requirements and achieve even more high-quality and intelligent sensing, TSMC has been working on multi-wafer stack solution, demonstrating new sensor architectures such as stacked pixel sensors, the smallest footprint for global shutter sensors, event-based RGB fusion sensors, and AI sensors with integrated memory.
  •  Display
    • TSMC is focusing on higher resolution and lower power consumption for many new applications, driven by 5G, AI, and AR/VR.
    • The next generation high-end OLED panel will require more digital logic and SRAM content, and a faster frame rate. To address this need, TSMC is bringing its HV technology down to 28nm generation for better energy efficiency and higher SRAM density.
    • TSMC’s leading µDisplay on silicon technology can deliver up to 10X pixel density to achieve the higher resolution needed for near-eye displays like those used in AR and VR.

You can see more detailed descriptions of TSMC’s specialty offerings of MEMs Technology, CMOS Image Sensor, eFlash, MS/RF, Analog, HV, and BCD HERE.

Also Read:

TSMC 2023 North America Technology Symposium Overview Part 1

TSMC 2023 North America Technology Symposium Overview Part 2

TSMC 2023 North America Technology Symposium Overview Part 3

TSMC 2023 North America Technology Symposium Overview Part 5

Posted on

TSMC 2023 North America Technology Symposium Overview Part 3

TSMC 2023 North America Technology Symposium Overview Part 3
by Daniel Nenni on 04-27-2023 at 6:00 am
Categories: Chiplet, Events, Foundries, TSMC

3DFabric Technology Portfolio

TSMC’s 3DFabric initiative was a big focus at the symposium, as it should be. I remember when TSMC first went public with CoWos the semiconductor ecosystem, including yours truly, let out a collective sigh wondering why TSMC is venturing into the comparatively low margin world of packaging. Now we know why and it is  absolutely brilliant!

In 2012 TSMC introduced, together with Xilinx, the by far largest FPGA available at that time, comprised of four identical 28 nm FPGA slices, mounted side-by-side, on a silicon interposer. They also developed through-silicon-vias (TSVs), micro-bumps and re-distribution-layers (RDLs) to interconnect these building blocks. Based on its construction, TSMC named this IC packaging solution Chip-on-Wafer-on-Substrate (CoWoS).

This building blocks-based and EDA-supported packaging technology has become the de-facto industry standard for high-performance and high-power designs. Interposers, up to three stepper fields large, allow combining multiple die, die-stacks and passives, side by side, interconnected with sub-micron RDLs. Most common applications were combinations of a CPU/GPU/TPU with one or more high bandwidth memories (HBMs).

In 2017 TSMC announced the Integrated FanOut technology (InFO). It uses, instead of the silicon interposer in CoWoS, a polyamide film, reducing unit cost and package height, both important success criteria for mobile applications. TSMC has already shipped tens of millions of InFO designs for use in smartphones.

In 2019 TSMC introduced the System on Integrated Chip (SoIC) technology. Using front-end (wafer-fab) equipment, TSMC can align very accurately, then compression-bond designs with many narrowly pitched copper pads, to further minimize form-factor, interconnect capacitance and power.

Today TSMC has 3DFabric, a comprehensive family of 3D Silicon Stacking and Advanced Packaging Technologies. Here are the TSMC related accomplishments from the briefing:

  • TSMC 3DFabric consists of a variety of advanced 3D Silicon Stacking and advanced packaging technologies to support a wide range of next-generation products:
    • On the 3D Si stacking portion, TSMC is adding a micro bump-based SoIC-P in the TSMC-SoIC® family to support more cost-sensitive applications.
    • The 2.5D CoWoS® platform enables the integration of advanced logic and high bandwidth memory for HPC applications, such as AI, machine learning, and data centers. InFO PoP and InFO-3D support mobile applications and InFO-2.5D supports HPC chiplet integration.
    • SoIC stacked chips can be integrated in InFO or CoWoS packages for ultimate system integration.
  • CoWoS Family
    • Aimed primarily for HPC applications that need to integrate advanced logic and HBM.
    • TSMC has supported more than 140 CoWoS products from more than 25
    • All CoWoS solutions are growing in interposer size so they can integrate more advanced silicon chips and HBM stacks to meet higher performance requirements.
    • TSMC is developing a CoWoS solution with up to 6X reticle-size (~5,000mm2) RDL interposer, capable of accommodating 12 stacks of HBM memory.
  • InFO Technology
    • For mobile applications, InFO PoP has been in volume production for high-end mobile since 2016 and can house larger and thicker SoC chips in smaller package form factor.
    • For HPC applications, the substrateless InFO_M supports up to 500 square mm chiplet integration for form factor-sensitive applications.
  • 3D Silicon stacking technologies
    • SoIC-P is based on 18-25μm pitch μbump stacking and is targeted for more cost-sensitive applications, like mobile, IoT, client, etc.
    • SoIC-X is based on bumpless stacking and is aimed primarily at HPC applications. Its chip-on-wafer stacking schemes feature 4.5 to 9μm bond pitch and has been in volume production on TSMC’s N7 technology for HPC applications.
    • SoIC stacked chips can be further integrated into CoWoS, InFo, or conventional flip chip packaging for customers’ final products.
  • 3DFabric™ Alliance and 3Dblox Standard
    • At last year’s Open Innovation Platform®(OIP) Forum, TSMC announced the new3DFabric™ Alliance, the sixth OIP alliance after the IP, EDA, DCA, Cloud, and VCA alliances, to facilitate ecosystem collaboration for next-generation HPC and mobile designs by:
      • Offering 3Dblox Open Standard,
      • Enabling tight collaboration between memory and TSMC logic, and
      • Bringing Substrate and Testing Partners into Ecosystem.
    • TSMC introduced 3Dblox™ 1.5, the newest version of its open standard design language to lower the barriers to 3D IC design.
      • The TSMC 3Dblox is the industry’s first 3D IC design standard to speed up EDA automation and interoperability.
      • 3Dblox™ 1.5 adds automated bump synthesis, helping designers deal with the complexities of large dies with thousands of bumps and potentially reducing design times by months.
      • TSMC is working on 3Dblox 2.0 to enable system prototyping and design reuse, targeting the second half of this year.

Above is an example of how TSMC 3DFabric technologies can enable an HPC chip. It also supports my my opinion that one of the big values of the Xilinx acquisition by AMD was the Xilinx silicon team. No one knows more about implementing advanced TSMC packaging solutions than Xilinx, absolutely.

Also Read:

TSMC 2023 North America Technology Symposium Overview Part 1

TSMC 2023 North America Technology Symposium Overview Part 2

TSMC 2023 North America Technology Symposium Overview Part 4

TSMC 2023 North America Technology Symposium Overview Part 5

 

Posted on

TSMC 2023 North America Technology Symposium Overview Part 2

TSMC 2023 North America Technology Symposium Overview Part 2
by Daniel Nenni on 04-26-2023 at 8:00 pm
Categories: Events, FinFET, Foundries, TSMC
8 Comments

TSMC N3 Update 2023

The next topic I would like to cover is an update to the TSMC process node roadmap starting with N3. As predicted, N3 will be the most successful node in the TSMC FinFET family. The first version of N3 went into production at the end of last year (Apple) and will roll out with other customers in 2023. There is a reported record amount of N3x design starts in process and from what I have heard from the IP ecosystem, that will continue.

Not only is N3 easy to design to, the PPA and yield is exceeding expectations. While I’m hearing good things about N2 I still think the mainstream chip designers will stick to N3 for quite some time and the ecosystem agrees.

Meanwhile the competition is still working on 3nm. Intel 3 for foundry customers is still in process and Samsung 3nm was skipped by all. I still have not heard of a successful tape-out to Samsung 3nm from a customer name that I recognize.

Here are the TSMC N3 accomplishments from the briefing:

  • N3 is TSMC’s most advanced logic technology and entered volume production in the fourth quarter of 2022 as planned; N3E follows one year after N3 and has passed technology qualification and achieved the performance and yield targets.
  • Compared with N5, N3E offers 18% speed improvement at the same power, 32% power reduction at the same speed, a logic density of around 6X, and a chip density of around 1.3X.
  • N3E has received the first wave of customer product tape-outs and will start volume production in the second half of 2023.
  • Today, TSMC is introducing N3P and N3X to enhance technology values and offer additional performance and area benefits while preserving design rule compatibility with N3E to maximize IP reuse.
  • For the first 3 years since inception, the number of new tape-outs for N3 and N3E is 5 to 2X that of N5 over the same period, because of TSMC’s technology differentiation and readiness.
  • N3P: Offers additional performance and area benefits while preserving design rule compatibility with N3E to maximize IP reuse. N3P is scheduled to enter production in the second half of 2024, and customers will see 5% more speed at the same leakage, 5-10% power reduction at the same speed, and 1.04X more chip density compared with N3E.
  • N3X: Expertly tuned for HPC applications, N3X provides extra Fmax gain to boost overdrive performance at a modest trade-off with leakage. This translates to 5% more speed versus N3P at drive voltage of 1.2V, with the same improved chip density as N3P. N3X will enter volume production in 2025.
  • Today, TSMC introduced the industry’s first Auto Early technology on 3nm, called N3AE. Available in 2023, N3AE offers automotive process design kits (PDKs) based on N3E and allow customers to launch designs on the 3nm node for automotive applications, leading to the fully automotive-qualified N3A process in 2025.

TSMC N3 will be talked about for many years. Not only did TSMC execute as promised, the competition did not, so it really is a perfect semiconductor storm. The result being a very N3 focused industry ecosystem that will be impossible to beat, absolutely.

Here are the TSMC N2 accomplishments from the media briefing:

  • N2 volume production is targeted for 2025; N2P and N2X are planned for 2026.
  • Performance of the nanosheet transistor has exceeded 80% of TSMC’s technology target while demonstrating excellent power efficiency and lower Vmin, which is a great fit for the energy-efficient compute paradigm of the semiconductor industry.
    • TSMC has exercised N2 design collateral in the physical implementation of a popular ARM A715 CPU core to measure PPA improvement: Achieved a 13% speed gain at the same power, or 33% power reduction at the same speed at around 0.9V, compared to the N3E high-density 2-1 fin standard cell.
  • Part of the TSMC N2 technology platform, a backside power rail provides additional speed and density boost on top of the baseline technology.
    • The backside power rail is best suited for HPC products and will be available in the second half of 2025.
    • Improves speed by more than 10-12% from reducing IR drop and signal RC delays.
    • Reduces logic area by 10-15% from more routing resources on the front side.

Remember, N2 is nanosheets, which, unlike FinFETs, is not open source technology so this is really going to be a challenge for design and the supporting ecosystem which gives TSMC a very strong advantage. TSMC also mentioned what follows nanosheets which I found quite interesting. I’m sure we will hear more about this at IEDM 2023:

  • Transistor architecture has evolved from planar to FinFET and is about to change again to nanosheet.
  • Beyond nanosheet, TSMC sees vertically stacked NMOS and PMOS, known as CFET, as one of the key process architecture choices going forward.
    • TSMC estimates the density gain would fall between 5 to 2X after factoring in routing and process complexity.
  • Beyond CFET, TSMC made breakthroughs in low dimensional materials such as carbon nanotubes and 2D materials which could enable further dimensional and energy scaling.

For the record, TSMC has deployed 288 distinct process technologies and manufactured 12,698 products for 532 customers and counting. There is no stopping this train so you might as well jump on with the rest of the semiconductor industry.

Also Read:

TSMC 2023 North America Technology Symposium Overview Part 1

TSMC 2023 North America Technology Symposium Overview Part 3

TSMC 2023 North America Technology Symposium Overview Part 4

TSMC 2023 North America Technology Symposium Overview Part 5

Posted on

TSMC 2023 North America Technology Symposium Overview Part 1

TSMC 2023 North America Technology Symposium Overview Part 1
by Daniel Nenni on 04-26-2023 at 6:00 pm
Categories: 5G, AI, Events, Foundries, TSMC

Advanced Technology Roadmap

The TSMC 2023 North America Technology Symposium happened today so I wanted to start writing about it as there is a lot to cover. I will do summaries and other bloggers will do more in-depth coverage on the technology side in the coming weeks. Having worked in the fabless semiconductor ecosystem the majority of my 40 year semiconductor career and writing about it since 2009 I may have a different view of things than the other media sources so stay tuned.

First some items from the opening presentation. As I have mentioned before, AI is driving the semiconductor industry and North America is leading the way with a reported 43% of the world wide AI business. With AI you have 5G since tremendous amounts of data have to be both processed and communicated from the edge to the cloud and back again and again and again.

Due to this tremendous industry driver, TSMC expects the global semiconductor market to approach $1 trillion by 2030 as demand surges from HPC-related applications with 40% of the market, smartphone at 30%, automotive at 15%, and IoT at 10%.

Of course in 2023 we will experience a revenue pothole which C.C. Wei joked about. C.C. said he would not give a forecast this year since he was wrong in saying TSMC would again experience double digit growth in 2023. It is now expected to be single digit decline and it could be even worse than that if you believe other industry sources. Since the TSMC forecast is derived from customer forecasts they were wrong too, there is plenty of blame to share and joke about, which C.C. did.

I still blame the pandemic for the horrible forecasting of late, truly a black swan event. Personally I think the foundry business and TSMC specifically is in the strongest position today so I have no worries whatsoever.

I had flashbacks to when Morris Chang spoke at the symposiums during the C.C. Wei presentation. I see a lot of Morris in C.C. but I also see a very focused man who is not afraid to ask for purchase orders. I also see a much stronger competitive nature in C.C. and I would never want to be on the wrong side of that, absolutely.

“Our customers never stop finding new ways to harness the power of silicon to create innovations that shall amaze the world for a better future,” said Dr. C.C. Wei, CEO of TSMC. “In the same spirit, TSMC never stands still, and we keep enhancing and advancing our process technologies with more performance, power efficiency, and functionality so their pipeline of innovation can continue flowing for many years to come.”

I sometimes tell my family that I don’t want to talk about my accomplishments because it will seem like bragging and I’m much too humble to brag. This is actually true with TSMC so here are some of their accomplishments from the briefing:

  • Together with partners, TSMC created over 12,000 new, innovative products, on approximately 300 different TSMC technologies in 2022.
  • TSMC continues to invest in advanced logic technologies, 3DFabric, and specialty technologies to provide the right technologies at the right time to empower customer innovation.
  • As our advanced nodes evolve from 10nm to 2nm, our power efficiency has grown at a CAGR of 15% over a span of roughly 10 years to support the semiconductor industry’s incredible growth.
  • The CAGR of TSMC’s advanced technology capacity growth will be more than 40% during the period of 2019 to 2023.
  • As the first foundry to start volume production of N5 in 2020, TSMC continues to improve its 5nm family offerings by introducing N4, N4P, N4X, and N5A.
  • TSMC’s 3nm technology is the first in the semiconductor industry to reach high-volume production, with good yield, and the Company expects a fast and smooth ramping of N3 driven by both mobile and HPC applications.
  • In addition, to push scaling to enable smaller and better transistors for monolithic SoCs, TSMC is also developing 3DFabric technologies to unlock the power of heterogeneous integration and increase the number of transistors in a system by 5X or more.
  • TSMC’s specialty technology investment experienced more than 40% CAGR from 2017 to 2022. By 2026, TSMC expects to grow specialty capacity by nearly 50%.

The two customer CEO presentations that followed C.C. were quite a contrast. ADI has been a long and trusted TSMC customer where as Qualcomm has been foundry hopping since the beginning of fabless time. I remember working with QCOM on a 40nm design that was targeted to four different fabs. TSMC did the hard work first then it went to UMC, SMIC, and Chartered for high volume manufacturing.  QCOM has a new CEO and TSMC has CC Wei so that may change. The benefits of being loyal to TSMC have grown dramatically since the planar days so we shall see.

Also Read:

TSMC 2023 North America Technology Symposium Overview Part 2

TSMC 2023 North America Technology Symposium Overview Part 3

TSMC 2023 North America Technology Symposium Overview Part 4

TSMC 2023 North America Technology Symposium Overview Part 5