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Future Semiconductor Technology Innovations

Future Semiconductor Technology Innovations
by Tom Dillinger on 07-19-2022 at 6:00 am
Categories: Events, Foundries, TSMC
3 Comments

2D metals

At the recent VLSI Symposium on Technology and Circuits, Dr. Y.J. Mii, Senior Vice President of Research and Development at TSMC, gave a plenary talk entitled, “Semiconductor Innovations, from Device to System”.  The presentation offered insights into TSMC’s future R&D initiatives, beyond the current roadmap.  The associated challenges of the technologies being investigated were also highlighted.  This article summarizes Dr. Mii’s compelling presentation.

Technology Drivers

Dr. Mii began with a forecast for future end market growth, emphasizing both the need for continued gains in high-performance compute throughput and the focus on power efficiency.  For the HPC requirements, he shared a “digital data boom” forecast, shown in the figure below.  For example, a “smart” factory will be expected to collect, monitor, and analyze 1 petabyte of data per day.

The role of machine learning (training and inference) support for the applications above is likewise anticipated to expand as well, putting further demands on the HPC throughput requirements.  Dr. Mii commented that these HPC requirements will continue to drive R&D efforts to increase logic density, both in the semiconductor process roadmap and advanced (heterogeneous) packaging technology.

The relentless focus on power efficiency is exemplified by the slide below.

The architecture shown illustrates not only the extent to which 5G (and soon, 6G) will be pervasive in the devices we use, but also in the operation of “edge data centers”.  As with HPC applications, the influence of machine learning algorithms will be pervasive, and needs to be focused on power efficiency.

Recent Technology Innovations

Before describing some of TSMC’s R&D projects, Dr. Mii provided a brief summary of recent semiconductor process technology innovations.

  • EUV lithography introduction at node N7+
  • SiGe pFET channel for improved carrier mobility
  • Design Technology Co-optimization (DTCO)

Dr. Mii emphasized how process technology development has evolved to incorporate much greater emphasis on DTCO, that evaluating tradeoffs between process complexity and design improvements has become an integral part of process development.  He highlighted recent adoption of contact-over-active-gate and single diffusion break process steps as examples.  He added, “DTCO efforts are not exclusive to logic design – memories and analog circuitry are a key facet to DTCO assessments, as well.”

  • nanosheets (at node N2)

TSMC will be transitioning from FinFET devices to a nanosheet device topology at the N2 process node.

Future Semiconductor Technology Innovations

Dr. Mii then described several semiconductor technology R&D efforts for future application requirements.

  • CFET (complementary FET)

After decades of planar FET device technologies, FinFETs have experienced a considerable longevity as well, from N16/N12 to N7/N6 to N5/N4 to N3/N3E.  It will be interesting to see how process nodes based on nanosheet devices evolve.  After nanosheets, Dr. Mii focused on the introduction of CFET devices.

As illustrated in the figure below, a CFET process retains the benefits of the gate-all-around nanosheets, yet fabricates the pFET and nFET devices vertically.  (In the figure, the pFET is on the bottom, and the nFET is on the top.)

In the cross-section of the inverter logic gate depicted above, the common gate input and common drain nodes of the two devices are highlighted.

The figure below expands upon the process development challenges introduced by the CFET device stacking, especially the need for high aspect ratio etching and related metal trench fill for the vertical connectivity highlighted above.

NB:   Different researchers investigating CFET process development have been pursuing two paths:  a “sequential” process where pFET and nFET devices are realized using a upper thinned substrate for top device fabrication that is bonded to the starting substrate after bottom device fabrication, with an intervening dielectric layer;  a “monolithic” process where there is a single set of epitaxial layers used for all devices on the substrate.  There are tradeoffs in process complexity and thermal budgets, device performance optimizations (with multiple substrate materials in the sequential flow), and cost between the two approaches.  Although Dr. Mii did not state specifically, the comments about high AR etching and metal fill would suggest that TSMC R&D is focused on the monolithic CFET process technology.

  • 2D Transistor Materials

There is active research evaluating “post-silicon” materials for the field-effect transistor channel.  As shown below, as the device gate length and body thickness of the channel are reduced, 2D materials offer the potential for both improved carrier mobility and sub-threshold slope (with lower leakage currents and the potential for lower VDD operation).

One of the major challenges to 2D process development is to provide low contact resistance connections to the device source/drain nodes.  Dr. Mii shared results previously published by TSMC researchers highlighting the evaluation of bismuth (Bi) and antimony (Sb) – a 5X reduction in Rc over previously published work was achieved, as shown below.

  • BEOL interconnect architecture

Scaling of the back-end-of-line interconnect is encountering the challenge that existing (damascene) Cu wires are less effective.  The Cu diffusion barrier (e.g., TaN) and adhesion liner (e.g., Ta) in the damascene trench occupies an increasing percentage of the scaled wire cross-section.  The Cu deposition grain size is constrained as well, resulting in greater electron scattering and higher resistivity.  The figure below highlights TSMC R&D efforts to introduce a new (subtractive-etched) BEOL metallurgy.

With a subtractive metal process, new opportunities for fabrication of the dielectric between wires are introduced – the figure above illustrates an “air gap” cross-section within the adjacent dielectric.

  • 2D conductors

Beyond a replacement for Cu as the BEOL interconnect described above, TSMC R&D is investigating the potential for 2D conductors.

The figure above shows a cross-section of 2D conductor layers, and the resulting conductivity benefits compared to a comparable Cu wire thickness.

(Dr. Mii did not elaborate on the specific materials being evaluated.  For example, there are a number of transition metal compounds that demonstrate high carrier mobility in a 2D crystalline topology, as well as the capability to stack these layers which are bound by van der Waals forces.)

Summary

Dr. Mii concluded his talk with the slide shown above.  Future system designs will leverage:

  • increased transistor density, as exemplified by CFET devices (and DTCO-focused process development)
  • new interconnect materials
  • increasing integration of heterogeneous functionality in advanced packaging, including both chiplets and HBM stacks in 2.5D and 3D configurations
  • new methodologies for system design partitioning, physical implementation, and electrical/thermal analysis

It couldn’t be a more exciting time to be in the industry, whether as a designer or a process technology engineer.

-chipguy

Also read:

TSMC 2022 Technology Symposium Review – Advanced Packaging Development

TSMC 2022 Technology Symposium Review – Process Technology Development

Three Key Takeaways from the 2022 TSMC Technical Symposium!

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TSMC 2022 Technology Symposium Review – Advanced Packaging Development

TSMC 2022 Technology Symposium Review – Advanced Packaging Development
by Tom Dillinger on 06-27-2022 at 6:00 am
Categories: Events, Foundries, TSMC
2 Comments

3D blox

TSMC recently held their annual Technology Symposium in Santa Clara, CA.  The presentations provide a comprehensive overview of their technology status and upcoming roadmap, covering all facets of the process technology and advanced packaging development.  This article will summarize the highlights of the advanced packaging technology presentations – a previous article covered the process technology area.

General

TSMC has merged their 2.5D and 3D packaging offerings into a single brand – “3D Fabric”.  The expectations are that there will be future customers that pursue both options to provide dense, heterogeneous integration of system-level functionality – e.g., both “front-end” 3D vertical assembly, combined with “back-end” 2.5D integration.

Technically, the 2.5D integration of SoCs with “3D” high-bandwidth memory HBM stacks is already a combined offering.  As illustrated above, TSMC is envisioning a much richer mix of topologies in the future, combining 3D SoIC with 2.5D CoWoS/InFO as part of very complex heterogeneous system designs.

As with the process technology presentations at the Symposium, the packaging technology updates were pretty straightforward – an indication of successful, ongoing roadmap execution.  There were a couple of specific areas representing new directions that will be highlighted below.

Of particular note is the TSMC investment in an Advanced System Integration fab, which will support the 3D Fabric offerings, providing full assembly and test manufacturing capabilities.

2.5D packaging

There are two classes of 2.5D packaging technologies – “chip-on-wafer-on-substrate” (CoWoS) and “integrated fanout” (InFO).

(Note that in the figure above, some of the InFO offerings are denoted by TSMC as “2D”.)

The key initiative for both these technologies is to continue to expand the maximum package size, to enable a larger number of die (and HBM stacks) to be integrated.  As an example, the fabrication of the interconnect layers on a silicon interposer (CoWoS-S) requires “stitching” multiple lithographic exposures – the goal is to increase the interposer size in term of multiples of the maximum reticle dimensions.

  • CoWoS

CoWoS has expanded to offer three different interposer technologies (the “wafer” in CoWoS):

  • CoWoS-S
    • uses a silicon interposer, based on existing silicon wafer lithographic and redistribution layer processing
    • in volume production since 2012, >100 products for 20+ customers to date
    • the interposer integrates embedded “trench” capacitors
    • 3X max reticle size in development – to support a design configuration with 2 large SoC’s and 8 HBM3 memory stacks, with eDTC1100 (1100nF/mm**2)
  • CoWoS-R
    • uses an organic interposer for reduced cost
    • up to 6 redistribution layers of interconnect, 2um/2um L/S
    • 2.1X reticle size supporting one SoC with 2 HBM2 stacks in a 55mmX55mm package; 4X reticle size in development, with 2 SoCs and 2HBM2 in an 85mmX85mm package
  • CoWoS-L
    • uses a small silicon “bridge” inserted into an organic interposer, for high density interconnects between adjacent die edges (0.4um/0.4um L/S pitch)
    • 2X reticle size supports 2 SoCs with 6 HBM2 stacks 2023); 4X reticle size in development to support 12 HBM3 stacks (2024)

TSMC highlighted that they are working with the HBM standards group on the physical configuration of HBM3 interconnect requirements for CoWoS implementations.  (The HBM3 standard appears to have settled on the following for the stack definition:  capacity of 4GB w/four 8Gb die to 64GB w/sixteen 32Gb die; 1024-bit signal interface; up to 819GBps bandwidth.) These upcoming CoWoS configurations with multiple HBM3 stacks would provide tremendous memory capacity and bandwidth.

Also, in anticipation of much greater power dissipation in upcoming CoWoS designs, TSMC is working on appropriate cooling solutions, both improved thermal-interface-materials (TIM) between die and package, as well as transitioning from air to immersion cooling.

  • InFO

After accurate (face-down) placement orientation on a temporary carrier, die are encapsulated in a epoxy “wafer”.  Redistribution interconnect layers are added to the reconstituted wafer surface.  The package bumps are then connected directly to the redistribution layers.

There are InFO_PoP, InFO_oS, and InFO_B topologies.

As shown below, InFO_PoP denotes a package-on-package configuration, and is focused on integration of a DRAM package with a base logic die.  The bumps on the DRAM top die utilize through-InFO vias (TIV) to reach the redistribution layers.

  • InFO_PoP primarily for the mobile platform
  • over 1.2B units shipped since 2016

An issue with the InFO_PoP implementation is that currently the DRAM package is a custom design, and only able to be fabricated at TSMC.  There is an alternative InFO_B topology in development, where an existing (LPDDR) DRAM package is added on top, with assembly to be provided by an external contract manufacturer.

InFO_oS (on-substrate) enables multiple die to be encapsulated, with the redistribution layers and their microbumps connected to a substrate with TSVs.

  • in production for over 5 years, focus is on HPC customers
  • 5 RDL layers on the substrate, with 2um/2um L/S
  • the substrate enables a large package footprint, currently at 110mm X 110mm with plans for greater sizes
  • 130um C4 bump pitch

As depicted above, InFO_M is an alternative to InFO_oS, with multiple encapsulated die and redistribution layers, without the additional substrate + TSVs (< 500mm**2 package, production in 2H2022).

3D packaging

InFO-3D

There is a 3D stacked package technology that utilizes micro-bumped die integrated vertically with redistribution layers and TIVs, focused on the mobile platform.

3D SoIC

The more advanced vertical-die stacked 3D topology packaging family is denoted as “system-on-integrated chips” (SoIC).  It utilizes direct Cu bonding between the die, at an aggressive pitch.

There are two SoIC offerings – “wafer-on-wafer” (WOW) and “chip-on-wafer” (COW).  The WOW topology integrates a complex SoC die on a wafer providing deep trench capacitor (DTC) structures for optimal decoupling.  The more general COW topology stacks multiple SoC die.

The process technologies qualified for SoIC assembly are shown in the table below.

Design Enablement for 3DFabric, including 3Dblox

As illustrated in the upper right corner of the 3D Fabric image above, TSMC is envisioning complex system design-in-package implementations, combining both 3D SoIC and 2.5D technologies.

The resulting complexity in the design flow is great, as highlighted above, with advanced thermal, timing, and SI/PI analysis flows required (which can also deal with the model data volume).

To enable the development of these system-level designs, TSMC has collaborated with EDA vendors on three major design flow initiatives:

  • improved thermal analysis, using a coarse-grained plus fine-grained approach)
  • hierarchical static timing analysis
    • individual die are represented by an abstracted model, to reduce the total (multi-corner) data analysis complexity 
  • front-end design partitioning

To help accelerate the front-end design partitioning of a complex system, TSMC has pursued an initiative denoted as “3Dblox”.

The goal is to break down the overall physical package system into modular components, which are then integrated.  The module categories are:

  • bumps/bonds
  • vias
  • caps
  • interposers
  • die

These modules would be incorporated into any of the SoIC, CoWoS, or InFO package technologies.

Of specific note is that TSMC is driving an effort to enable 3D Fabric designs to use various EDA tools – that is, to complete physical design with one EDA vendor tool, and (potentially) use different EDA vendor products for support for timing analysis, signal integrity/power integrity analysis, thermal analysis.

3Dblox appears to take the concept of “reference flows” for SoCs to a new level, with TSMC driving interoperability between EDA vendor data models and formats.  The overall 3Dblox flow capability will be available in 3Q2022.  (A preliminary step – i.e., automated routing of redistribution signals on InFO – will be the first feature released.)

Clearly, TSMC is investing extensively in advanced packaging technology development and (especially) new fabrication facilities, due to the anticipated growth in both 2.5D and 3D configurations.  The transition from HBM2/2e to HBM3 memory stacks will result in considerable performance benefits to system designs utilizing CoWoS 2.5 technology.  Mobile platform customers will expand the diversity of InFO multi-die designs.  The adoption of complex 3DFabric designs combining both 3D and 2.5D technologies will no doubt increase, as well, leveraging TSMC’s efforts to “modularize” the design elements to accelerate system partitioning, as well as their efforts to enable a broad set of EDA tools/flows to be applied.

-chipguy

Also Read:

TSMC 2022 Technology Symposium Review – Process Technology Development

Three Key Takeaways from the 2022 TSMC Technical Symposium!

Inverse Lithography Technology – A Status Update from TSMC

Posted on

TSMC 2022 Technology Symposium Review – Process Technology Development

TSMC 2022 Technology Symposium Review – Process Technology Development
by Tom Dillinger on 06-22-2022 at 5:00 am
Categories: Events, Foundries, TSMC
7 Comments

finFLEX

TSMC recently held their annual Technology Symposium in Santa Clara, CA.  The presentations provided a comprehensive overview of their status and upcoming roadmap, covering all facets of process technology and advanced packaging development.  This article will summarize the highlights of the process technology updates – a subsequent article will cover the advanced packaging area.

First, here is a brief overview of some of the general observations and broader industry trends, as reported by C.C. Wei, TSMC CEO.

General

  • “This year marks TSMC’s 35th anniversary. In 1987, we had 258 employees in one location, and released 28 products across 3 technologies.  Ten years later, we had 5,600 employees, and released 915 products across 20 technologies.  This year in 2022, we have 63,000 employees, and will release 12,000 products across 300 technologies.” 
  • “From 2018 to 2022, the volume of 12” (equivalent) wafers has had an annual CAGR exceeding 70%. In particular, we are seeing a significant increase in the number of ‘big die’ products.”  (>500mm**2)
  • “In 2021, TSMC’s North America business segment shipped more than 7M wafers and over 5,500 products. There were 700 new products tapeouts (NTOs).  This segment represents 65% of TSMC’s revenue.”
  • “Our gigafab expansion plans have typically involved adding two new ‘phases’ each year – that was the case from 2017-2019. In 2020, we opened six new phases, including our advanced packaging fab.  In 2021, there were seven new phases, including fabs in Taiwan and overseas – advanced packaging capacity was added, as well. In 2022, there will be 5 new phases, both in Taiwan and overseas.” 
    • N2 fabrication: Fab20 in Hsinchu
    • N3: Fab 18 in Tainan
    • N7 and N28: Fab22 in Kaohsiung
    • N28: Fab16 in Nanjing China
    • N16, N28, and specialty technologies: Fab23 in Kumanoto Japan (in 2024)
    • N5 in Arizona (in 2024)
  • “TSMC has 55% of the worldwide installed base of EUV lithography systems.”
  • “We are expanding our capital equipment investment significantly in 2022.” (The table below highlights the considerable jump in cap equipment planned expenditures.)
  • “We are experiencing stress in the manufacturing capacity of mature process nodes. In 35 years, we have never increased the capacity of a mature node after a subsequent node has ramped to high volume manufacturing – that is changing.”
  • “We continue to invest heavily in “intelligent manufacturing”, focusing on precision process control, tool productivity, and quality. Each gigafab handles 10M dispatch orders per day, and optimizes tool productivity.  Each gigafab generates 70B data points daily to actively monitor.” 

For the first time at the Symposium, a special “Innovation Zone” on the exhibit floor was allocated. The recent product offerings from a number of start-up companies were highlighted.  TSMC indicated, “We have increased our support investment to assist small companies adopt our technologies.  There is a dedicated team that focuses on start-ups.  Support for smaller customers has always been a focus.  Perhaps somewhere in this area will be the next Nvidia.”

Process Technology Review

With a couple of exceptions discussed further on, the process technology roadmap presentations were somewhat routine – that’s not a bad thing, but rather an indication of ongoing successful execution of prior roadmaps.

The roadmap updates were presented twice, once as part of the technology agenda, and again as part of TSMC’s focus on platform solutions.  Recall that TSMC has specifically identified four “platforms” that individually receive development investment to optimize the process technology offerings:  mobile; high-performance computing (HPC); automotive; and IoT (ultra-low power).  The summaries below merge the two presentations.

N7/N6

  • over 400 NTOs by year-end 2022, primarily in the smartphone and CPU markets
  • N6 offers transparent migration from N7, enabling IP re-use
  • N6RF will be the RF solution for upcoming WiFi7 products
  • there is an N7HPC variant (not shown in the figure above), providing ~10% performance improvement at overdrive VDD levels

For N6, logic cell-based blocks can be re-implemented in a new library for additional performance improvements, achieving a major logic density improvement (~18%).

N5/N4

  • in the 3rd year of production, with over 2M wafers shipped, 150 NTOs by year-end 2022
  • mobile customers were the first, followed by HPC products
  • roadmap includes ongoing N4 process enhancements
  • N4P foundation IP is ready, interface IP available in 3Q2022 (to the v1.0 PDK)
  • there is an N5HPC variant (not shown in the figure above, ~8% perf improvement, HVM in 2H22)

As with the N7/N6, N4 provides “design re-use” compatibility with N5 hard IP, with a cell-based block re-implementation option.

The complexity of SoC designs for the automotive segment is accelerating.  There will be an N5A process variant for the automotive platform, qualified to AEC-Q100 Grade 1 environmental and reliability targets (target date: 2H22).  The N5A automotive process qualification involves both modeling and analysis updates (e.g., device aging models, thermal-aware electromigration analysis).

N3 and N3E

  • N3 will be in HVM starting in the second half of 2022
  • N3E process variant in HVM one year later; TSMC is expecting broad adoption across mobile and HPC platforms
  • N3E is ready for design start (v0.9 PDK), with high yield on the standard 256Mb memory array qualification testsite
  • N3E adds the “FinFLEX” methodology option, with three different cell libraries optimized for different PPA requirements (more at the end of this article)

Note that N3 and N3E are somewhat of an anomaly to the prior TSMC process roadmap.  N3E will not offer a transparent migration of IP from N3.  The N3E offering is a bit of a “correction”, in that significant design rule changes to N3 were adopted to improve yield.

TSMC’s early-adopter customers push for process PPA updates on an aggressive timeline, whether an incremental, compatible variant to an existing baseline (e.g., N7 to N6, N5 to N4), or for a new node.  The original N3 process definition has a good pipeline of NTOs, but N3E will be the foundation for future variants.

N2

  • based on a nanosheet technology, target production date: 2025
  • compared to N3E, N2 will offer ~10-15% performance improvement (@iso-power, 0.75V) or ~25-30% power reduction (@iso-perf, 0.75V); note also the specified operating range in the figure above down to 0.55V
  • N2 will offer support for a backside power distribution network

Parenthetically, TSMC is faced with the dilemma that the requirements of the different platforms have such a broad range of targets for power, performance, and area/cost.  As was noted above, N3E is addressing these targets with different libraries, incorporating a different number of fins that define the cell height.  For N2 library design, this design decision is replaced by a process technology decision on the number of vertically-stacked nanosheets throughout (with some allowed variation in the device nanosheet width).  It will be interesting to see what TSMC chooses to offer for N2 to cover the mobile and HPC markets, in terms of the nanosheet topology.  (The image below from an earlier TSMC technical presentation at the VLSI 2022 Conference depicts 3 nanosheets.)

NB:  There are two emerging process technologies being pursued to reduce power delivery impedance and improve local routability – i.e., “buried” power rail (BPR) and “backside” power distribution (BSPDN).  The initial investigations into offering BPR have quickly expanded to process roadmaps that integrate full BSPDN, like N2.  Yet, it is easy to get the two acronyms confused.

Specialty Technologies

TSMC defines the following offerings into a class denoted as “specialty technologies”:

  • ultra-low power/ultra-low leakage (utilizing an ultra-high Vt device variant)
    • requires specific focus on ultra-low leakage SRAM bitcell design
    • N12e in production, N6e in development (focus on very low VDD model support)
  • (embedded) non-volatile memory
    • usually integrated with a microcontroller (MCU), typically in a ULP/ULL process
    • RRAM
      • requires 2 additional masks, embedded in BEOL (much lower cost than the 12 masks for eFlash)
      • 10K write cycles (endurance specification), ~10 years retention @125C
    • MRAM
      • 22MRAM in production, focus is on improving endurance
      • 16MRAM for Automotive Grade 1 applications in 2023
  • power management ICs (PMIC)
    • based on bipolar-CMOS-DMOS (BCD) devices: 40BCD+, 22BCD+
    • for complex 48V/12V power domains
    • requires extremely low device R_on
  • high voltage applications (e.g., display drivers, using N80HV or N55HV)
  • analog/mixed-signal applications, requiring unique active and passive structures (e.g., precision thin-film resistors and low noise devices, using N22ULL and N16FFC)
  • MEMS (used in motion sensors, pressure sensors)
  • CMOS image sensors (CIS)
    • pixel size of 1.75um in N65, 0.5um in N28, transitioning to N12FFC
  • radio frequency (RF), spanning from mmWave to longer wavelength wireless communication; the upcoming WiFi7 standard was highlighted

“The transition from WiFi6 to WiFi7 will require a significant increase in area and power, to support the increased bandwidth requirements – e.g., 2.2X area and 2.1X power.  TSMC is qualifying the N6RF offering, with a ~30-40% power reduction compared to N16RF.  This will allow customers currently using N16RF to roughly maintain existing power/area targets, when developing WiFi7 designs.”

The charts below illustrate how these specialty technologies are a fundamental part of platform products – e.g., smartphones and automotive products.  The characteristic process nodes used for these applications are also shown.

Although the focus of smartphone development tends to be on the main application processor, the chart below highlights the extremely diverse requirements for specialty technology offerings, and their related features.  In the automotive area, the transition to a “zonal control” architecture will require a new set of automotive ICs.

N3E and FinFLEX

The FinFLEX methodology announcement was emphasized, with TSMC indicating “FinFLEX will offer full-node scaling from N5.”

As FinFET technology nodes have scaled – i.e., from N16 to N10 to N7 to N5 – the fin profile and drive current_per_micron have improved significantly.  Standard cell library design has evolved to incorporating fewer pFET and nFET fins that define the cell height (specified in terms of the number of horizontal metal routing tracks).  As illustrated above, the N5 library used a 2-2 fin definition – that is, 2 pFET fins and 2 nFET fins to define the cell height.  (N16/N12 used a 3-3 configuration.)

The library definition for N3E was faced with a couple of issues.  Mobile and HPC platform applications are increasingly divergent, in terms of their PPA (and cost) goals.  Mobile products focus on circuit density to integrate more functionality and/or reduced power, with less demanding performance improvements.  HPC is much more focused on maximizing performance.

As a result, N3E will offer three libraries, as depicted in the figure above:

    • an ultra low power library  (cell height based on a 1-fin library)
    • an efficient library (cell height based on a 2-fin library)
    • a performance library (cell height based on a 3-fin library)

The figure below is from TSMC’s FinFLEX web site, illustrating the concept (link).

Now, offering multiple libraries for integration on a single SoC is not new.  For years, processor companies have developed unique “datapath” and “control logic” library offerings, with different targets for:  cell heights, circuit performance, routability (i.e., max cell area utilization), and distinct logic offerings (e.g., wide AND-OR gates for datapath multiplexing).  Yet, the physical implementation of SoC designs using multiple libraries relied upon a consistent library per design block.

The unique nature of the FinFLEX methodology is that multiple libraries and multiple track heights will be intermixed within a block. 

After the TSMC Symposium, additional information became available.  A block design will alternate rows for the two libraries.  For example, a 3:2 block design will have alternate row heights accommodating cells from the 3-fin and 2-fin library designs.  A 2:1 block design will have alternate rows for cells from the 2-fin and 1-fin libraries.

TSMC indicated, “Different cell heights (in separate rows) are enabled in one block to optimize PPA.  FinFLEX in N3E incorporates new design rules, new layout techniques, and significant changes to EDA implementation flows.”

There will certainly be more information to come about FinFLEX and the changes to the general design flow.  Off-hand, there will need to be new approaches to:

    • physical synthesis
      • how will synthesis improve timing on a critical signal
      • will synthesis strive to provide a netlist with a balanced ratio of cells from the two libraries for the alternating rows

For example, to improve timing on a highly-loaded signal, synthesis would typically update a cell assignment in the library to the next higher drive strength – e.g., NAND2_1X to NAND2_2X.

With FinFLEX, additional options are available with the second library – e.g., whether an update to NAND2_1X_2fin would use NAND2_2X_2fin or NAND2_1X_3fin.  Yet, if the latter is chosen, the new cell will need to be “re-balanced” to a different row in the block floorplan.  The effective changes in performance and input/output wire loading for these choices are potentially quite complex to estimate during physical synthesis.

The cell selection options get even more intricate when considering specific flop cells to use, given not only the differences in clock-to-Q delays, but also the setup and hold time characteristics, and input clock loading.   When would it be better for individual flop bits in a register to use different output drive strengths in the same library (and be placed locally) versus having register bits re-balanced to a row corresponding to a different library selection?

With an alternating row configuration, the assumption is that there will be an even mix of cells from the two libraries.  Yet, the synthesis of a block may only require a small percentage of “high-performance” cells to meet timing objectives.   An output netlist without a balanced mix of library cells may have low overall utilization, suggesting a uniform row, single-library block floorplan may be suitable instead.  This may result in iterations in the chip floorplan (and likely, revisions in the power distribution network, as well).

    • sub-block level IP integration

Blocks often contain a number of small hard IP macros, such as register files (typically provided by a register file generator).  With non-uniform row heights, the algorithms in the generator become more complex, to align the power continuity between the macro circuits and the cell rows.  And, there will be placement restriction rules that will need to be added to the hard IP models.

    • timing/power optimizations during physical design

Similarly to the physical synthesis block construction options, there will be difficult decisions on cell selection during the timing and power optimization steps in the physical design flow.  For example, if a cell can reduce its assigned drive strength to save power while still meeting timing, would a change in library selection, and thus row re-balancing, be considered?  Would the corresponding changes in the cell placement negate the optimization?

and, last but most certainly not least,

    • Will there be new EDA license costs to enable N3E FinFLEX?

(Years ago, the CAD department manager at a previous employer of mine went viral at the license cost adder to enable placement and routing for multipatterning requirements.  Given the significant EDA investment required to support FinFLEX, history may repeat itself with additional license feature costs.)

The FinFLEX methodology definitely offers some intriguing options.  It will be extremely interesting to see how this approach evolves.

Analog design migration automation

Lastly, TSMC briefly highlighted work they are pursuing in the area of assisting designers migrate analog/mixed-signal circuits and layouts to newer process nodes.

Specifically, TSMC has defined a set of “analog cells”, with the capability to take an existing schematic, re-map to a new node, evaluate circuit optimizations, and migrate layouts, including auto-placement and (PG + signal) routing.

The definition of the analog cell libraries for N5/N4 and N3E are complete, with N7/N6 support to follow.  TSMC showed an example of an operational transconductance amplifier (OTA) that had been through the migration flow.

Look for more details to follow. (This initiative appears to overlap with comparable features available from EDA vendor custom physical design platforms.)

A subsequent article will cover TSMC’s advanced packaging announcements at the 2022 Technology Symposium.

-chipguy

Also read:

Three Key Takeaways from the 2022 TSMC Technical Symposium!

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Three Key Takeaways from the 2022 TSMC Technical Symposium!

Three Key Takeaways from the 2022 TSMC Technical Symposium!
by Daniel Nenni on 06-16-2022 at 12:10 pm
Categories: Events, Foundries, TSMC
18 Comments

TSMC Technology Roadmap 2022

The TSMC Technical Symposium is today so I wanted to give you a brief summary of what was presented. Tom Dillinger will do a more technical review as he has done in the past. I don’t want to steal his thunder but here is what I think are the key takeaways. First a brief history lesson.

The history of TSMC Technology Development with 12 key milstones:

In 1987 TSMC was founded with the creation of the PurePlay business model.

In 1999 TSMC was the first foundry to offer 0.18 micron copper technology.

2001 brought the first foundry reference design flow. I participated in this with multiple EDA and IP vendors and I can tell you first hand that TSMC spent a huge amount of money creating the massive EDA and IP ecosystem we enjoy today.

In 2011 TSMC brought HKMG 28nm to the fabless ecosystem. Other foundries faltered at 28nm so this was a record breaking node for TSMC.

2012 brought CoWos, the first heterogenous 3DIC test vehicle.

In 2014 TSMC delivered the first fully functional FinFET networking processor which began the FinFET era that TSMC dominates today.

In 2015 TSMC qualified InFo, the advanced 3DIC packaging technology.

In 2018 TSMC delivered the most advanced logic technology (N7) available to all.

In 2020 TSMC lead the industry with N5 EUV based logic technology.

In 2021 TSMC launched N4P, N4X, and N6RF.

In 2022 TSMC will launch what will be the most advanced N3 process nodes covering a wide range of vertical markets. N3 will also break the record for tapeouts in a 5 year period, my opinion.

And last but not least, in 2022 TSMC announced the next generation process technology for the masses (N2).

Takeaway #1

TSMC will continue to invest in mature node and specialty technologies with a 1.5x capacity expansion from 2021 to 2025 which includes Fabs F14P8 (Tianan), F16 P1B (Nanjing), F22 P2 (Kaohsiung) and fab F23 P1 (Kumamoto Japan).

TSMC also announced an Integrated Specialty Technology Platform for NVM, HV, Sensor, PMIC, ULP/ULL, analog, and RF technology. Tom Dillinger will go into more detail here.

Takeaway #2

TSMC will continue scaling N3. N3 is on track for HVM in 2H 2022. N3E follows in 2H 2023 with improved performance/power and low process complexity for both mobile and HPC applications.

N3E PPA versus N5 comes in at 18% speed at same power or 34% power reduction at same speed, and a 1.6x logic density increase.

More importantly, TSMC announced FinFlex: Ultimate Design Flexibility for N3. TSMC just published a blog on FinFlex with more detail. Tom Dillinger will also have his say on this so stay tuned. Bottom line: you can change fin configurations to further optimize designs for area, speed, and power.

Takeaway #3

TSMC will use nanosheet transistors for N2. Not a huge surprise since Intel and Samsung have already made announcements but there is much more here than meets the eye. N2 PPA vs N3E is expected to be a 15% speed improvement at the same power or 25-30% power improvement at the same speed, and > 1.1x density. N2 is expected in 2025.

TSMC also discussed device architecture futures which included Nanosheet, CFET, 2D TMD, and CNT. We will be writing more about this later.

Bottom line: One thing we must all remember is that there is a distinct difference between a PurePlay and an IDM foundry. TSMC must produce the most cost effective, wide ranging process technologies with a fully supported ecosystem for hundreds of products. IDM foundries can pick and choose what is important and don’t have to worry about wafer margins. Semiconductor insiders know this but the media does not so expect continued misinformation in the coming days, absolutely.

So many more things were presented. If you have questions post them in the comments section and I will get the answers for you, absolutely.

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TSMC N3 will be a Record Setting Node!

Intel and the EUV Shortage

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Inverse Lithography Technology – A Status Update from TSMC

Inverse Lithography Technology – A Status Update from TSMC
by Tom Dillinger on 06-02-2022 at 6:00 am
Categories: Events, Foundries, TSMC
6 Comments

ILT mask rules

“Inverse lithography technology (ILT) represents the most significant EDA advance in the last two decades.”  Danping Peng from TSMC made that assertion at the recent SPIE Advanced Lithography + Patterning Conference, in his talk entitled:  ILT for HVM:  History, Present, and Future.  This article summarizes the highlights of his insightful presentation.  Indeed, ILT has enabled improvements in the ability to print wafer-level features with improved fidelity.

ILT History

First, a brief review of the steps after design tapeout, associated with mask manufacture:

  • The mask shop applies optical proximity correction (OPC) or ILT algorithms to the mask data.
  • Mask data prep (MDP) will compose the OPC/ILT-generated data in a format suitable for the mask writer.
  • Mask writing has evolved from (an optically-based) pattern-generation shot exposure of the photoresist-coated mask blank to an e-beam based exposure. Both variable-shaped beam (VSB) and multiple-beam ask writing systems are available.  (More on this shortly.)
  • Mask inspection steps include:
    • critical dimension (CD) metrology (CD-SEM)
    • mask review using an aerial image measurement system (e.g., Zeiss AIMS)
    • mask defect repair

The mask then proceeds to the fab, where a wafer-level print will be subjected to similar steps:  CD-SEM dimensional evaluation, wafer inspection and defect analysis.

The need for mask correction algorithms is highlighted in the figure below.

As the printed dimensions on the wafer scaled with successive process nodes, the fidelity of the image – i.e., the difference between the target image and the printed wafer contour – became poor.  Corrections to the layout design data were needed.

The original approach to generating mask updates were denoted as optical proximity corrections (OPC).  Individual segments in the (rectilinear) design data were bisected at appropriate intervals, and the sub-segments were moved, typically using a rule-based algorithm.  Rectangular serifs were added at shape corners – both expanded segments at outside corners and reduced at inside corners.  (Colorful names were given to the OPC results – e.g., “hammerheads”, “dogbones”.)

Subsequently, OPC algorithms added sub-resolution assist features (SRAF) to the mask data.  These are distinct shapes from the original design, whose dimension is intentionally chosen so as not to print at the wafer photoresist resolution, but to provide the appropriate (constructive and destructive) interference due to optical diffraction at the edges of the design shapes.

As shown in the figures above and below, ILT algorithms make a fundamentally different assumption, utilizing curvilinear mask data for corrections and SRAFs.  The figure below illustrates the key differences between the edge-based nature of OPC and the pixel-based ILT algorithm.

How ILT Works

Danping used the following two figures to illustrate how ILT works.  The first figure below is a high-level flowchart, providing the comprehensive (ideal) iterative loop between mask data generation and post-etch wafer-level metrology.  (More on this full loop shortly.)

The figure below provides more detail on the ILT flow.  Two adjacent shapes are used for illustration.

A three-dimensional representation of the illumination intensity is computed.  An error function is calculated, with a weighted sum of constituent elements.  Each weight is multiplied by a factor related to the difference between the calculated print image and the wafer target across the pixel field.

The error function could include contributions from a variety of printed image characteristics:

  • nominal dimension (print-to-target difference)
  • modeled three-dimensional resist profile
  • pixel light intensity outside the target area to be suppressed
  • sensitivity to illumination dose and focus variations

Iterative optimizations are pursued to reduce the magnitude of this error function.  Note that the figure above mentions gradient-based optimization to reduce the error function calculated form a difference between a model prediction and a target – the similarities of ILT to machine learning methods are great, as Danping highlighted in the Futures portion of his talk.

Current ILT Adoption and Challenges

There have been hurdles to ILT adoption over the past two decades.  Danping reviewed these challenges, and how they are being addressed.

  • mask write time

The curvilinear (pixel-based) ILT mask data provide improved depth-of-focus over conventional OPC methods.  Yet, the corresponding data complexity results in a major increase in the e-beam shot count to write the mask, using variable size beam (VSB) technology.

Danping explained, “When ILT was first being pursued, there were no multiple beam mask writers.  As a result, it took days to expose an ILT mask with a VSB system.  Now, with multiple-beam systems, the mask write time in essentially constant, around 8 hours.” 

Note that there are “moderate constraints” applied for the ILT data generation to assist with this speed-up – e.g., minimum design rules for SRAF area/space/CD, maximum limits on the curvature of the shapes data.

  • ILT mask data generation time

“The first adoption of ILT was by memory foundries.”, Danping indicated.  “The highly repetitive nature of their layouts, with some careful crafting, results in a reduced number of repeating patterns.” 

ILT adoption for logic designs has been slower.  Danping elaborated on some of the challenges:

    • long computational runtime (“20X slower than OPC”)
    • mask data rules checking technology for curvilinear edges has lagged
    • improvements in exposure systems have improved image resolution (e.g., 193 to 193i) and dose uniformity, reducing the ILT advantages

ILT algorithms for model generation and error function + gradient computation is dominated by matrix operations.  To address the runtime challenge, ILT code has been ported to GPU-based computation resources.  This provides “a 10X speed-up over strictly CPU-based computation”, according to Danping.

To address the mask data validation challenge, the SEMI Curvilinear Task Force is working on a data representation that will serve as a standard format for model interchange.  (This is also driven by the curvilinear design layout data associated with silicon photonics structures.)  The figure below illustrates new “rule definitions” that will be part of mask data checking.

Danping provided the following observation on the market opportunity for ILT relative to improvements in exposure systems, “ILT can be used to squeeze more performance from an existing tool.”  In that sense, ILT may enable extended utilization of existing scanners.

Danping shared a forecast that “Both EUV and 193i masks will commonly incorporate curvilinear shapes in 2023.”  (Source:  eBeam Initiative)

ILT Future

Danping offered three forecasts for ILT technology.

  • adoption of deep learning techniques

As mentioned above, the ILT algorithm shares a great deal in common with the computation and optimization techniques of deep neural network methods.  The figure below illustrates how deep learning could be adopted.

“A trained deep learning model could be used to generate mask data, followed by a small number of ILT iterations.  ILT mask data could be derived in 15% of the previous runtime.”, Danping mentioned.

  • increased use of curvilinear design data

In addition to silicon photonics structures, the opportunity to use curvilinear data directly in circuit layouts at advanced process nodes may soon be adopted.  (Consider the case where metal “jumpers” are used on layer Mn+1 to change routing tracks for a long signal on layer Mn.)  The industry support for curvilinear data representation would enable this possibility, although it would also have a major impact on the entire EDA tool flow.

  • a full “inverse etch technology” (IET) flow to guide ILT

An earlier figure showed a “full loop” flow for mask data generation, incorporating post-etch results.  Rather than basing the ILT error function on computational models of the resist expose/develop profile, the generation of the cost function would be derived from the final etched material image model, as illustrated below.

(DOM:  dimension of mask;  ADI:  after photoresist develop inspection;  AEI:  after etch inspection)

Significant effort would be needed to construct the “digital twin” models for etch processes.  However, the benefits of a comprehensive mask data-to-process flow optimization would be great.

Summary

ILT will clearly expand beyond its current (memory-focused) applications.  The industry efforts to support a standard for efficient and comprehensive curvilinear data representations – for both mask and design data – will help to accelerate the corresponding EDA and fabrication equipment enablement.  As Danping put it, “It is not a question of if, but when and how many layers will use ILT.”

-chipguy

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TSMC N3 will be a Record Setting Node!

TSMC N3 will be a Record Setting Node!
by Daniel Nenni on 05-19-2022 at 6:00 am
Categories: Events, Foundries, TSMC
5 Comments

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With the TSMC Technical Symposium coming next month there is quite a bit of excitement inside the fabless semiconductor ecosystem. Not only will TSMC give an update on N3, we should also hear details of the upcoming N2 process.

Hopefully TSMC will again share the number of tape-outs confirmed for their latest process node. Given what I have heard inside the ecosystem, N3 tape-outs will be at a record setting number. Not only has Intel joined TSMC for multi-product high volume N3 production, it has been reported that Qualcomm and Nvidia will also use N3 for their leading edge SoCs and GPUs. In fact, it would be easier to list the companies that will not use TSMC for 3nm but at this point I don’t know of any. It is very clear that TSMC has won the FinFET battle by a very large margin, absolutely.

“The most outstanding news of TSMC in 2021 was the success in attracting more new business from Intel, while being able to maintain great relationships with existing customers such as AMD, Qualcomm and Apple. With its 3 nm N3 entering volume production later in 2022 with good yield and 2 nm N2 development being on track for volume production in 2025, TSMC is expected to continue its technology leadership to support its customer innovation and growth. Thanks to the demand of bleeding-edge technologies, TSMC’s foundry leadership position seems to have become even more concrete in recent years.”

Samuel Wang, analyst with Gartner, from their recent analyst report: “Market Share Analysis: Semiconductor Foundry Services, Worldwide, 2021” that went live on May 9, 2022.

Now that live events have started up again in Silicon Valley the information flow inside the semiconductor ecosystem has returned to pre pandemic levels. I have attended (6) live semiconductor events thus far in 2022 and have several more to go before the biggest foundry event The 2022 TSMC Technology Symposium which kicks off at the Santa Clara Convention Center on June 16 followed by events in Europe (6/20), China (6/30), and Taiwan (6/30).

SemiWiki has covered the TSMC events for the past 11 years and we will have bloggers attending this year as well. This is the number one networking event for TSMC customers, partners, and suppliers so I can assure you there will be a lot to write about.

Here is the most recent update on technology development from TSMC:

  • TSMC’s 3nm technology development is on track with good progress, and the company has developed complete platform support for HPC and smartphone applications. TSMC N3 is entering volume production in the second half of 2022, with good yield.
  • TSMC N3E will further extend its 3nm family, with enhanced performance, power, and yield. The Company also observed a high level of customer engagement at N3E, and the volume production for N3E is scheduled for one year after N3
  • Faced with the continuous challenge to significantly scale up semiconductor computing power, TSMC has focused its R&D efforts on contributing to customers’ product success by offering leading-edge technologies and design solutions. In 2021, the company started risk production of 3nm technology, the 6th generation platform to make use of 3D transistors, while continuing the development of 2nm, the leading-edge technology in the semiconductor industry today. Furthermore, the company’s research efforts pushed forward with exploratory studies for nodes beyond 2nm. TSMC’s 2nm technology has entered the technology development phase in 2021, with development being on track for volume production in 2025.

TSMC also introduced N4P process in October 2021, a performance-focused enhancement of the 5nm technology platform. N4P delivers an 11% performance boost over the original N5 technology and a 6% boost over N4. Compared to N5, N4P will also deliver a 22% improvement in power efficiency as well as a 6% improvement in transistor density.

TSMC introduced N4X process technology at the end of 2021, which offers a performance boost of up to 15% over N5, or up to 4% over the even faster N4P at 1.2 volt. N4X can achieve drive voltages beyond 1.2 volt and deliver additional performance. TSMC expects N4X to enter risk production by the first half of 2023. With N5, N4X, N4P, and N3/N3E, TSMC customers will have multiple and compelling choices for power, performance, area, and cost for their products.

Bottom line: This will be one of the more exciting TSMC Technical Symposiums. TSMC N2 has been under NDA while the IDM foundries have been leaking details about their upcoming 2nm processes. This is a classic marketing move, when you don’t have a competing product today, talk about tomorrow.

One thing we should all remember is that all of the leading semiconductor companies, with the exception of Samsung, are collaborating with TSMC. The TSMC ecosystem consists of 100s of customers, partners, and suppliers and it is like no other. If you think another foundry will have a higher yielding 2nm process that can support a wide range of products you would be wrong.

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Intel and the EUV Shortage

Intel and the EUV Shortage
by Scotten Jones on 04-13-2022 at 10:00 am
Categories: Foundries, Intel Foundry, Lithography, Samsung Foundry, Semiconductor Services, TechInsights, TSMC
12 Comments

Slide1

In my “The EUV Divide and Intel Foundry Services” article available here, I discussed the looming EUV shortage. Two days ago, Intel announced their first EUV tool installed at their new Fab 34 in Ireland is a tool they moved from Oregon. This is another indication of the scarcity of EUV tools.

I have been tracking EUV system production at ASML to-date and forecasted output looking forward. I have also been looking at fabs that have been built and equipped and fab announcements to estimate the future requirement for EUV tools.

My approach is as follows:
  • List out each EUV capable fab by company with process type/node and capacity by year. I estimate how many EUV exposures are required for each process and convert this to an EUV layer count forecast by year (exposures x capacity).
  • For each year I look at the type(s) of EUV tools ASML produces and estimate the throughput by tool type for logic and memory processes.
  • Outset the required tools by time to account for the time between a tool delivery and the tool being in production.
Some notes about demand:
  • Intel currently has 3 development fabs phases that are EUV capable and 1 EUV capable production fab although only the development fab has EUV tools installed. Intel is building 8 more EUV capable production fabs.
  • Micron Technology has announced they are pulling in EUV from the one delta node to one gamma. Micron’s Fab 16-A3 in Taiwan is under construction to support EUV.
  • Nanya has talked about implementing EUV.
  • SK Hynix is in production of one alpha DRAM using EUV for approximately 5 layers and have placed a large EUV tool order with ASML.
  • Samsung is using EUV for 7nm and 5nm logic and ramping up 3nm. Samsung also has 1z DRAM in production with 1 EUV layer and 1 alpha ramping up with 5 EUV layers. Fabs in Hwaseong and Pyeongtaek have EUV tools with significant expansion in Pyeongtaek underway and the planned Austin logic fab will be EUV.
  • TSMC has fab 15 phases 5, 6, and 7 running 7nm EUV processes. Fab 18 phase 1, 2, and 3, are running 5nm with EUV. 5nm capacity ended 2021 at 120k wpm and has been projected to reach 240k wpm by 2024. Fab 21 in Arizona will add an additional 20k wpm of 5nm capacity. 3nm is ramping in Fab 18 phases 4, 5, and 6 and is projected to be a bigger node than 5nm. Fab 20 phases 1, 2, 3, and 4, are in the planning stages for 2nm and another 2nm site is being discussed.

Based on all of these fabs and our estimated timing and capacity we get figure 1.

Figure 1. EUV Supply and Demand.

 Figure 1 leads to a couple of key observations:

  • There will be more demand for EUV tools than supply in 2022, 2023, and 2024. Our latest forecast is a shortage of 18 tools in 2022, 12 tools in 2023 and 20 tools in 2024.
  • Looking at the logic companies where the bulk of EUV demand is, TSMC has the most EUV systems with roughly one half of the systems in the world, Samsung is next and then Intel. Of the three companies Intel will likely be the most constrained by the supply of EUV tools. It wasn’t that long ago that Intel was pushing out EUV tool orders, likely a mistake they wish they could take back.

In summary, over at least the next three years, leading edge EUV based capacity will be constrained by the scarcity of EUV tools with Intel likely to be hardest hit.

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Can Intel Catch TSMC in 2025?

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Can Intel Catch TSMC in 2025?

Can Intel Catch TSMC in 2025?
by Scotten Jones on 04-11-2022 at 6:00 am
Categories: FinFET, Foundries, Intel Foundry, Lithography, Semiconductor Services, TechInsights, TSMC
11 Comments

Slide6

At the ISS conference held from April 4th through 6th I presented on who I thought would have the leading logic technology in 2025. The following is a write up of that presentation.

ISS was a virtual conference in 2021 and I presented on who currently had logic leadership and declared TSMC the clear leader. Following that conference, I did a lot of calls for investment firms, and I was often asked when Intel would catch TSMC, my answer was unless TSMC stumbled, never.

A year later the foundries are stumbling, and Intel is accelerated, can Intel catch up?

I reviewed some Intel history, discussed their leadership throughout the 2000s and then how in the 2010s they began to fall behind, I discussed why I thought this happened.

I have previously published on Intel’s issues here.

The bottom line is 2014 through 2019 Samsung and TSMC each introduced 4 nodes while Intel introduced 2, the Intel nodes were bigger individual density jumps but when you chain together the 4 foundry jumps, they increased density more than Intel and took the lead. Figure 1. summarizes this.

Figure 1. Foundries Versus Intel in the 2010s.

Figure 1 only illustrates the “nodes” from Intel, they weren’t standing still, for 14nm they released 5 versions all with the same density but with progressively improving performance and for 10nm they released 4 versions, once again with the same density but improving performance (note the last version has now been renamed 7nm).

By 2020 Samsung and TSMC both had 5nm in production and compared to Intel 10nm they are denser processes. TSMC had taken a lager jump from 7nm to 5nm then Samsung and was the clear leader with the densest process, smallest SRAM cell size and the industries first silicon germanium FinFET. Figure 2. summarizes this.

Figure 2. 2020 Comparison.

In 2021 the foundries have slowed down.

Samsung 3nm has encountered yield issues and we believe in 2022 their 3GAE (early) process will be used almost exclusively for internal products with 3GAP (performance) being released to external customers in 2023. Samsung chose to go to Horizontal Nanosheets (HNS) for 3nm (a type of gate all around process Samsung calls Multibridge). I believe HNS production issues are still being worked out and Samsung’s interest in being first to HNS has led to delays and poor yields.

TSMC did risk starts of their FinFET based 3nm process in 2021 but production is now pushed to late 2022 with products in the industry in 2023. In 2019 TSMC had risk starts of 5nm and by late 2020 iPhones were shipping with TSMC 5nm parts, for 3nm we won’t see iPhones until 2023. TSMC has also reduced the density for this process from an original 1.7x target to ~1.6X with reduced performance targets.

While Samsung and TSMC were experiencing delays, Intel announced, “Intel Accelerated”, an aggressive roadmap of 4 nodes in 4 years. This is truly accelerated when you consider 14nm took 3 years and 10nm took 5 years. I was frankly skeptical of this when it was announced but at the recent investors event Intel is pulling in the most advanced 18A process from 2025 to 2024!

Our view from now to 2025 is as follows:

2022 – Intel 4nm process, Intel’s first EUV use with a 20% performance improvement over 7nm. Intel had formerly talked about a 2X density improvement for this generation but is now just saying a “significant density improvement”, we are estimating 1.8X. Samsung 3nm will likely be for internal use only with a 1.35X density improvement, 35% better performance at the same power and 50% lower power at the same performance. The density improvement is not very impressive but the performance and power improvements are, likely due to adoption HNS. TSMC 3nm is FinFET based and will provide an ~1.6X density improvement with 10% better performance at the same power and 25% lower power at the same performance.

2023 – Intel 3nm process with 18% better performance, denser libraries and more EUV use. We estimate a 1.09X density improvement making this more of a half node. Samsung 3GAP should be available to external customers and TSMC 3nm parts should appear in iPhones.

2024 – in the first half Intel 20A (20 angstrom = 2nm) process is due with a 15% performance improvement. This will be Intel’s first HNS (they call it RibbonFET) and they will also introduce back side power delivery (they call this PowerVia). The backside power delivery addresses IR power drops while making front side interconnect easier. We are estimating a 1.6X density improvement. In the second half of 2024 Intel’s 18A process is due with a 10% performance improvement. We are estimating a 1.06X density improvement making this another half node. This process has been pulled in from 2025 and Intel says they have delivered test devices to customers.

2025 – Samsung 2nm is due in late 2025, we expect it to be a HNS and because it will be Samsung’s third generation HNS (counting 3GAE as the 1st generation and GAP as the 2nd generation) and their previous generations have been relatively less dense we are forecasting a 1.9X density jump. TSMC has not announced their 2nm process yet other than to say they expect to have the best process in 2025. We may see 2nm in 2024 but for now we have it placed in 2025, we expect a HNS process and are estimating a 1.33X density improvement. We believe the density improvement will be modest because it is TSMC’s first HNS and because the 3nm process is so dense that further improvements will be more difficult.

Figure 3 illustrates how Intel may “flip the script” on the foundries by doing 4 nodes while the foundries do 2.

Figure 3. Density jumps.

We can now look at how Intel, Samsung, and TSMC will compare in density out to 2025. We also added IBM’s 2nm research device based on their 2nm announcement. Figure 4. presents both density versus year and node.

Figure 4. Transistor Density Trends.

 From figure 4 we expect TSMC to maintain the density lead through 2025.

The most complex part of our analysis is illustrated in figure 5 where we compare performance. It is very difficult to compare processes to each other for performance without having the same design run on different processes and this rarely happens. The way we generated this plot is as follows:

  • The Apple A9 process was run in both Samsung 14nm and TSMC 16nm and Tom’s hardware found the same performance for both versions, we have normalized performance at this node to 1 for both Samsung and TSMC.
  • From the 14/16nm node through 3nm we have used the companies announced performance improvements to plot relative performance. For 2nm we have used our own projections.
  • We don’t have any designs that ran on Intel processes and either Samsung or TSMC. However, AMD and Intel both make X86 microprocessors and AMD microprocessors on TSMC 7nm process have competed with Intel 10nm Superfin processors with similar performance and we have set Intel 10SF to the same performance as TSMC 7nm. This is not ideal and assumes that both companies have done an equally good job on design but is the best available comparison. We have then scaled all the other Intel nodes from the 10SF based on Intel’s announcements.
  • Once again, we have place IBM’s 2nm on this chart based on their 2nm announcement.

Figure 5. Relative Performance Trends.

 Our analysis leads us to believe Intel may take the performance lead both on a year basis and a node basis. This is consistent with Intel’s stated goal of taking the “performance per watt lead”. Assuming TSMC is referring to density their statement that they will have the best process in 2025 could also be true.

In conclusion we believe Intel has been able to significantly accelerate their process development at a time when the foundries are struggling. Although we don’t expect Intel to regain the density lead over the time period studied, we do believe they could retake the performance lead. We should get another good read on progress by the end of 2022 when we see whether Intel 4nm comes out on time.

Also Read:

TSMC’s Reliability Ecosystem

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TSMC’s Reliability Ecosystem

TSMC’s Reliability Ecosystem
by Tom Dillinger on 04-06-2022 at 10:00 am
Categories: Events, Foundries, TSMC

AC accelerated stress conditions

TSMC has established a leadership position among silicon foundries, based on three foundational principles:

  • breadth of technology support
  • innovation in technology development
  • collaboration with customers

Frequent SemiWiki readers have seen how these concepts have been applied to the fabrication and packaging technology roadmaps, which continue to advance at an amazing cadence.  Yet, sparse coverage has typically been given to TSMC’s focus on process and customer product reliability assessments – these principles are also fundamental to the reliability ecosystem at TSMC.

At the recent International Reliability Physics Symposium (IRPS 2022), Dr. Jun He, Vice-President of Corporate Quality and Reliability at TSMC, gave a compelling keynote presentation entitled:  “New Reliability Ecosystem: Maximizing Technology Value to Serve Diverse Markets”.  This article provides some of the highlights of his talk, including his emphasis on these principles.

Technology Offerings and Reliability Evaluation

The figures above highlight the diverse set of technologies that Dr. He’s reliability team needs to address.  The reliability stress test methods for these technologies vary greatly, from the operating voltage environment to unique electromechanical structures.

Dr. He indicated, “Technology qualification procedures need to be tailored toward the application.  Specifically, the evaluation of MEMS technologies necessitates unique approaches.  Consider the case of an ultrasound detector, where in its end use the detector is immersed in a unique medium.  Our reliability evaluation methods need to reflect that application environment.”

For more traditional microelectronic technologies, the reliability assessments focus on accelerating defect mechanisms, for both devices and interconnect:

  • hot carrier injection (HCI)
  • bias temperature instability (NBTI for pFETs, PBTI for nFETs)
  • time-dependent dielectric breakdown (TDDB)
  • electromigration (for interconnects and vias)

Note that these mechanisms are highly temperature-dependent.

As our understanding of the physics behind these mechanisms has improved, the approaches toward evaluating their impact to product application failure rates have also evolved.

Dr. He commented, “Existing JEDEC stress test standards are often based on mechanism acceleration using a DC Vmax voltage.  However, customer-based product qualification feedback did not align with our technology qualification data.  Typically, the technology-imposed operating environment restrictions were more conservative.”

This is of specific interest to high-performance computing (HPC) applications, seeking to employ boost operating modes at increased supply voltages (within thermal limits).

Dr. He continued, “We are adapting our qualification procedures to encompass a broader set of parameters.  We are incorporating AC tests, combining Vmax, frequency, and duty cycle variables.”

The nature of “AC recovery” in the NBTI/PBTI mechanism for device Vt shift has been recognized for some time, and is reflected in device aging models.  Dr. He added, “We are seeing similar recovery behavior for the TDDB defect mechanism.  We are aggressively pursuing reliability evaluation methods and models for AC TDDB, as well.”

The figure above illustrates the how the Vt shift due to BTI is a function of the duty cycle for the device input environment, as represented by the ratio of the AC-to-DC Vt difference.  The figure also highlights the newer introduction of a TDDB lifetime assessment for high-K gate dielectrics, as a function of input frequency and duty cycle.

Parenthetically, Dr. He acknowledged that end application product utilization can vary widely, and that AC reliability testing makes some usage assumptions.  He indicated that TSMC works with customer to establish appropriate margins for their operating environment.

Reliability Evaluation of New Device Types

TSMC has recently added resistive RAM (RRAM) and magneto-resistive RAM (MRAM) IP to their technology offerings.

The unique physical nature of the resistance change in the storage device for these technologies necessitates development of a corresponding reliability evaluation procedure, to establish retention and endurance specifications.  (For the MRAM technology, the external magnetic field immunity specification is also critical.)

For both these technologies, the magnitude and duration of the write current to the storage cell is a key design parameter.  The maximum write current is a crucial reliability factor.  For the MRAM example, a high write current through the magnetic tunnel junction to set/reset the orientation of the free magnetic layer in the storage cell degrades the tunnel barrier.

TSMC collaborates with customers to integrate write current limiting circuits within their designs to address the concern.  The figure below illustrates the write current limiter for the RRAM IP.

TSMC and Customer Collaboration Reliability Ecosystem

In addition to the RRAM and MRAM max write current design considerations, Dr. He shared other examples of customer collaborations, which is a key element of the reliability ecosystem.

Dr. He. shared the results of design discussions with customers to address magnetic immunity factors – the figure below illustrates cases where the design integrated a Hall effect sensor to measure the local magnetic field.  The feedback from the sensor can be used to trigger corrective actions in the write cycle.

The customer collaboration activities also extend beyond design for reliability (DFR) recommendations.  TSMC shares defect pareto data with customers.  Correspondingly, the TSMC DFR and design-for-testability (DFT) teams will partner with customers to incorporate key defect-oriented test screens into the production test flow.

Dr. He provided the example where block-specific test screens may be appropriate, as illustrated below.

Power management design approaches may be needed across the rest of the design to accommodate block-level test screens.

The figure below depicts the collaboration model, showing how customer reliability feedback is incorporated into both the test environment and as a driver for continuous improvement process (CIP) development to enhance the technology reliability.

Summary

At the recent IRPS, TSMC presented their reliability ecosystem, encompassing:

  • developing unique reliability programs across a wide breadth of technologies (e.g., MEMS)
  • developing new reliability methods for emerging technologies (e.g., RRAM, MRAM)
  • sharing design recommendations with customers to enhance final product reliability
  • collaborating closely with customers on DFR issues, and integrating customer feedback into DFT screening procedures and continuous improvement process focus

Reflecting upon Dr. He’s presentation, it is no surprise that these reliability ecosystem initiatives are consistent with TSMC’s overall principles.

-chipguy

Also read:

Self-Aligned Via Process Development for Beyond the 3nm Node

Technology Design Co-Optimization for STT-MRAM

Advanced 2.5D/3D Packaging Roadmap

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The EUV Divide and Intel Foundry Services

The EUV Divide and Intel Foundry Services
by Scotten Jones on 03-23-2022 at 10:00 am
Categories: Foundries, Intel Foundry, Lithography, Samsung Foundry, Semiconductor Services, TechInsights, TSMC
37 Comments

Intel IDM 2.0 Process Roadmap
The EUV Divide

I was recently updating an analysis I did last year that looked at EUV system supply and demand, while doing this I started thinking about Intel and their Fab portfolio.

If you look at Intel’s history as a microprocessor manufacturer, they are typically ramping up their newest process node (n), in volume production on their previous node (n-1) and ramping down the node before that (n-2 node). They don’t typically keep older nodes in production, for example, last year 10nm was n, 14nm was n-1 and 22nm was n-2. Intel had some 32nm capacity in Fab 11X but that has now been converted to a packaging Fab. This contrasts with someone like TSMC that built their first 130nm – 300mm fab in 2001 and is still running it plus their 90nm, 65nm, 40nm and 28nm fabs as well.

By the end of 2022 Intel should be ramping up their 4nm node, then in 2023 their 3nm node, and in 2024 their 20A (2nm) and 18A (1.8nm) nodes should ramp up. All of those are EUV based nodes and it would seem reasonable that by the end of 2024 Intel would have little use for non-EUV based processes for microprocessor production since their 7nm/10nm non-EUV nodes would be n-4/n-5 depending on how you treat 10nm/7nm.

If I look at Intel’s current and planned Fab portfolio, there are EUV capable fabs and older fabs that are unlikely to ever be used for EUV, in fact EUV tools require an overhead crane and many of Intel’s older fabs would likely require significant structural modifications to accommodate this, plus Intel is building 9 EUV based production fabs.

The following is a site by site look at Intel’s fabs:

  • New Mexico – Fab 11X phases 1 and 2 are Intel’s oldest production fabs and they are being converted to packaging Fabs. 11X-3D may continue to operate for 3D Xpoint. Intel recently discussed two more generations of 3D Xpoint and this is currently the only place to make it.
  • Oregon – Fab D1X phases 1, 2 and 3 now lead all of intel’s EUV based development and early production. Fabs D1C/25 and D1D are older development/production fabs that are unlikely to be converted to EUV and are currently being used for non-EUV production.
  • Arizona – Fabs 52 and 62 are EUV fabs under construction. Fab 42 is currently running non-EUV nodes but it was built as a EUV capable Fab and will likely be used for EUV someday. Fabs 12 and 32 are production fabs running non-EUV nodes and will likely never be converted to EUV.
  • Ireland – Fab 34 is an EUV fab under construction with equipment currently being moved in, this will likely be Intel’s first 4nm EUV node production site. Fabs 24 phases 1 and 2 are non-EUV production sites and will likely never be used for EUV (unless they get combined with Fab 34 at some point).
  • Israel – Fab 38 is an EUV fab under construction and will be a 4nm EUV node production site. Fabs 28 phases 1 and 2 are non-EUV node production and will likely never be used for EUV (unless they get combined with Fab 34 at some point).
  • Ohio – Silicon Heartland EUV based fabs 1 and 2 are in the planning stage.
  • Germany – Silicon Junction EUV based fabs 1 and 2 are in the planning stage.

In summary Intel is in various stages of running, building, or planning the following EUV based fabs, D1X phases 1, 2 and 3, Fabs 42, 52, and 62, Fab 34, Fab 38, Silicon heartland 1 and 2 and Silicon Junction 1 and 2. That is 3 development fabs/phases and 9 EUV based production fabs.

For non-EUV fabs still running, Intel has D1C/25, D1D, Fabs 12 and 32, Fab 24 phases 1 and 2, and Fab 28 phases 1 and 2. That is 8 non-EUV production Fabs. This really puts into perspective why Intel would want to get into the foundry business and support trailing edge processes. All these fabs can be used to produce any of Intel’s non EUV 10nm/7nm and larger processes plus likely with reasonable changes in equipment sets any of the processes they will be acquiring from the Tower acquisition.

Déjà vu all over again

Yogi Bera is famous for being humorously quotable and one of his famous quotes was “it is Déjà vu all over again”.

The last time Intel tried to get into the foundry business they failed to gain much traction. Foundry was still a second-class citizen at Intel, they didn’t have the design eco system and eventually exited the foundry business. One of the things that bothered me about Intel’s effort and in my opinion sent a message to foundry customers that foundry was second class was that Intel would develop a new process node, for example 32nm, they would introduce a high performance version for internal use and then a year later introduce the foundry (SOC) version.

Recently I saw an interview with Pat Gelsinger where he talked about 4nm being an internal process for Intel and then 3nm being the foundry version. 3nm is currently expected to come out approximately a year after 4nm. He then talked about 20A as an internal process and 18A as the foundry version. 18A is due to come out 6 to 9 months after 20A. I don’t think foundry customers will accept always being 6 to 12 months behind the leading edge and I think it sends the wrong message. He did say if a foundry customer really wanted to use 4nm they could, but he seemed to view 4nm and 20A as processes that should be tested internally before the next version is released more widely.

I do think Intel has an interesting opportunity. There is a shortage of foundry capacity at the trailing edge where Intel will likely be freeing up a lot of fab capacity and there is a shortage at the leading edge as well. In addition to that, there is a need for a second source at the leading edge. Samsung has a long history of over promising and under delivering on technology and yield. Companies like Qualcomm have repeatedly tried to work with Samsung, so they aren’t wholly dependent on TSMC and have been repeatedly forced back to TSMC. The latest example is the Qualcomm’s Snapdragon 8 gen 1 that is reported to have only 35% yield on Samsung’s 4nm node. If Intel can execute on their technology roadmap in a consistent basis with good yield, they can likely pick up a lot of second source and maybe even some primary source leading edge business particularly at Samsung’s expense. I could even see a company like Apple giving Intel some designs to strengthen their negotiating position with TSMC. I wouldn’t expect MediaTek, a Taiwan company located near TSMC, or AMD or NVDIA due to competitive concerns to work with Intel, but never say never.

EUV  shortage

As I mentioned at the outset it is a EUV supply and demand analysis I have been doing that triggered EUV gap ideas. As I outlined above Intel plans to build out and equip 9 EUV based Fabs. At the same time TSMC 5nm is widely believed to have ended 2021 at 120 thousand wafer per month capacity. TSMC has announced they expect to double the end of 2021 capacity on 5nm, by the end of 2024 and that is before the Arizona 5nm fab comes online. TSMC has talked about 3nm being an even bigger node than 5nm. TSMC has also started planning on a 4 phase 2nm fab with a second site in discussion. Samsung started using EUV for one layer on their 1z DRAM and then 5 layers on their 1a DRAM. Samsung is planning a new EUV based logic fab in Texas and is building out logic and DRAM capacity in Pyeongtaek. SK Hynix has started using EUV for DRAM, Micron has pulled in their DRAM EUV use from the delta to gamma generation and even Nanya is talking about using EUV for DRAM. This begs the question, will there be enough EUV tools available to support all these needs and my analysis is that there won’t.

In fact, I believe there will be demand for 20 more EUV tools than ASML can produce each of the next 3 years. To put that is perspective, ASML shipped 42 EUV systems in 2021 and is forecasting 55 system in 2022. Interestingly I saw a story today where Pat Gelsinger commented that he is personally talking to the CEO of ASML about system availability and admitted that EUV system availability will likely gate the ability to bring up all the new fabs.

I think another impact the EUV system shortage will drive is a different view of what layers to use EUV on. If a layer is currently done with multi-patterning more complex than double patterning EUV is generally cheaper. EUV also enables simpler design rules, more compact layouts, and potentially better performance. EUV will be even more important as the switch is made to horizontal nanosheets. I believe companies will be forced to prioritize EUV use to the layers where it has the most impact and continue to use multi-patterning for other layers.

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