IEDM: TSMC Ongoing Research on a CFET Process

IEDM: TSMC Ongoing Research on a CFET Process
by Paul McLellan on 12-18-2023 at 6:00 am

Screen Shot 2023 12 16 at 12.16.14 PM

I attended the recent International Electron Devices Meeting (IEDM) last week. Many of the sessions are too technical and too far away from high volume manufacture to make good topics for a blog post. As a Fellow from IBM said about 5nm at and earlier IEDM, “none of these ideas will impact 5nm. It takes ten years for a solution to from and IEDM paper to HVM. So 5nm will be something like FinFET with some sort of copper interconnect.” And so it turned out to be.

Often there are late submissions that IEDM accepts, usually from important manufacturers such as Intel or TSMC giving the first details of their next generation process. Unfortunately, over the years, these papers have got less informative and rarely include key measures such as the pitches on the most critical layers.

This year there was a late paper from TSMC titled Complementary Field-Effect Transistor (CFET) Demonstration at 48nm Gate Pitch for Future Logic Technology Scaling. A CFET is a CMOS process where the transistors are stacked vertically, rather than being in the same plane as with all previous logic processes: planar, FinFET, nanosheet field effect transistors (NSFET, also known as gate-all-around or GAA). The paper was by about 50 different authors that I’m not going to list, and was presented by Sandy Liao. She said it was “late news” since it is very recent work.

Presumably, TSMC will have a CFET process in the future, but this paper described early research on manufacturability. The process stacks the n-transistor on top of the p-transistor. In the Q&A Sandy was asked what motivated this decision. She said that it wasn’t cast in stone and could get changed in the future, but putting PMOS on the bottom makes handling strain easier. TSMC calls this monolithic CFET or mCFET.

CFET can create an area reduction of 1.5X to 2X, he said. There still has to be space for some vertical routing so you don’t usually get the full 2X you might expect from stacking the transistors. Previous studies of CFET manufacturing have used relaxed gate pitches, and don’t succeed in getting gate pitches around 50nm. So this TSMC study is the first that uses a gate pitch of 48nm, which Sandy said is “pertinent to industry-level advanced node scaling.”

To accomplish this, there is a middle dielectric isolation, inner spacer, and n/p source-drain isolation. This process provides a robust foundation for future mCFET advancement which will require further innovation and additional architectural features.

Here is a TEM demonstration of the mCFET. As I already said, the nFETs are on top and the pFETs on the bottom. Both types of transistors have the channel surrounded by a single metal gate.

Sandy said she would provide some details of the fabrication process “but not too much”. It is a 20-step flow, although obviously there are many sub-steps inside each step. For now, the process is expensive to manufacture she said in time engineers will solve that and so the process will have value. Below are the 20 steps.

By introducing a middle dielectric isolation, inner spacer, and n/p source-drain isolation, the vertically stacked transistors have a survival rate of over 90% with high on-state current and low leakage. There is a six-orders-of magnitude Ion/Ioff current ratio.

Sandy’s conclusion:
  • This is just the beginning, and there is a long way to go. But transistors in high volume cannot be worse than this. We need work hard to generate process features real yielding circuits with better characteristics.
  • This is just a study to pave the way for a practical process architecture that can fuel future logic technology, scaling, and PPAC advancement.
Also Read:

Analog Bits Leads the Way at TSMC OIP with High-Accuracy Sensors

TSMC N3E is ready for designs, thanks to IP from Synopsys

The True Power of the TSMC Ecosystem!


Arm Total Design Hints at Accelerating Multi-Die Activity

Arm Total Design Hints at Accelerating Multi-Die Activity
by Bernard Murphy on 11-02-2023 at 6:00 am

multi die

I confess I am reading tea leaves in this blog, but why not? Arm recently announced Arm Total Design, an expansion of their Compute Subsystems (CSS) offering which made me wonder about the motivation behind this direction. They have a lot of blue-chip partners lined up for this program yet only a general pointer to multi-die systems and what applications might drive the need. Neither Arm nor their partners will make this investment simply for PR value, so I have to assume there is building activity they are not ready to announce. I’m guessing that in a still shaky economy the big silicon drivers (in hyperscalers, AI, automotive, and maybe communication infrastructure) are already engaged in faster and managed cost paths to differentiated custom silicon, likely in multi-die systems.

Arm CSS and Total Design

I wrote about CSS recently. CSS N2, as Arm describes it, is customizable compute subsystem that is configured, verified, validated and PPA-optimized by Arm. Think of a multi-core cluster objective for which you don’t just get the Lego pieces (CPU core, coherent interconnect, memory subsystem, etc.) but a complete customizable compute subsystem configured with up to 64 Neoverse N2 cores, multiple DDR5/LP DDR5 channels and multiple PCIe/CXL PHY/controller. All verified, validated, and PPA-optimized by Arm to a target foundry and process.

Most recently Arm revealed Arm Total Design, a comprehensive ecosystem of ASIC design houses, IP vendors, EDA tool providers, foundries, and firmware developers – to accelerate and simplify the development of Neoverse CSS-based systems. EDA tools and IP are supplied by Cadence, Synopsys, Rambus and of course Arm, among others. Design services come from companies including ADTechnology, Alphawave Semi, Broadcom, Capgemini, Faraday, Socionext and Sondrel. For silicon process and packaging technology they call out Intel Foundry Services and TSMC (though not Samsung curiously, maybe they are still working on that partnership). And AMI is in this ecosystem to provide software and firmware support.

Reading the tea leaves

I recently blogged on a Synopsys-hosted panel on multi-die systems which suggested already at least 100+ such systems in development. Representatives from Intel and Samsung voiced no objections to that estimate. At the same time there was consensus that these are technologies still very much in development, requiring close collaboration between system company, EDA, IP, chiplet, design services, foundry, and software development. This is not something that an in-house design team, even a hyperscaler design team, can handle on their own.

Arm mentions multi-die chiplet SoC designs in their release though in a fairly general way as the next frontier. I suspect the need is more pressing. Multi-die systems are becoming essential to support state of the art designs driven by the latest AI innovations, especially around transformer-based techniques. We already know that datacenters are pushing these technologies, automotive applications are looking for differentiation in improved natural language recognition and visual transformers for better global recognition, even wireless infrastructure sees application for more intelligent services and more efficient radio communication.

All these applications are pushing higher levels of integration between compute, accelerators and memory, the kind of integration which requires multi-die packaging. This demands experts from foundries to design services to EDA tooling. We also need a ramp-up in available high value chiplet designs, where the press release suggests another hint. Socionext have built a multi-core CPU chiplet around CSS and are aiming it at TSMC 2nm for markets in server CPUs, data center AI edge servers, and 5/6G infrastructure.

More momentum behind multi-die systems. You can read the press release HERE.

 

 


Analog Bits Leads the Way at TSMC OIP with High-Accuracy Sensors

Analog Bits Leads the Way at TSMC OIP with High-Accuracy Sensors
by Mike Gianfagna on 10-18-2023 at 6:00 am

Analog Bits Leads the Way at TSMC OIP with High Accuracy Sensors

The 15th TSMC Open Innovation Platform® (OIP) event was held recently. This event is a focal point across the industry for cutting-edge development and industry-level collaboration. Appropriately, advanced packaging, paving the way for multi-die design was a focal point for the event. You can get a good overview of what was happening at OIP here. Beyond fab and packaging, there was a lot of talk about end markets, with automotive being a key growth area.  This is where I’d like to focus in this post – with another example of Analog Bits leadership in automotive grade sensors. Read on to see how Analog Bits leads the way at TSMC OIP with high-accuracy sensors.

Why It’s Important

According to recently published market research, the global automotive sensor market was worth $30.9 B in 2022, and is projected to grow at a CAGR of 7.3% to reach $ 61.4 B from 2023 to 2032. According to the research, “… substantial growth is due to the integration of sensors in vehicles to enhance safety, efficiency, and overall performance. Sensors are used in areas like advanced driver assistance systems (ADAS), engine management, and environmental monitoring. The market’s expansion is driven by regulatory mandates for vehicle safety, the rise of electric and autonomous vehicles, and consumer demand for innovative features.”

The report discussed the need for high-accuracy sensors in automotive designs. Everyone is getting into this market, including:

  • Robert Bosch GmbH
  • Continental AG
  • DENSO Corporation
  • Analog Devices, Inc.
  • Sensata Technologies, Inc.
  • Delphi Automotive PLC
  • Infineon Technologies AG
  • STMicroelectronics

The need for high-accuracy, automotive-grade sensors has become a white-hot item in vehicle design. It is against this backdrop that the work presented by Analog Bits is so important.

What Was Presented at OIP

Analog Bits has been at the forefront of precision analog IP for a long time. At OIP, the company showcased numerous IPs on TSMC’s industry-leading N5A process of its new high accuracy sensor and automotive grade, silicon proven designs at its booth. This development is part of Analog Bits’ broadening portfolio of mixed signal IP in advanced TSMC 3nm, 4nm, and 5nm processes. The company announced that design kits are available now.

Mahesh Tirupattur, executive vice president at Analog Bits weighed in with the following official comments:

“As we work with leading edge automotive customers on advanced FinFET processes, thermal issues continue to be a concern and need for multiple instances of sensors continues. Furthermore, many applications cannot have additional test costs associated with trimming for higher accuracy. We have been working on designs for improving un-trimmed accuracy in FinFETs and reducing the area of the sensors, and we are pleased to demonstrate working silicon of these higher accuracy sensors on N5A process at our booth at OIP.”

Mahesh is a force in this industry. You can review his incredible ride at Analog Bits here. Analog Bits has quite a deep technical bench. The president and CTO of Analog Bits, Alan Rogers gave a presentation at OIP about on-die power management IP’s, another very important topic. Let’s look at what Alan presented.

Alan’s Presentation at OIP

Alan Rogers

Alan Rogers has been at Analog Bits for over 25 years, and he’s been working with transistors for over 55 years. In his own words, he’s getting quite good at it. Alan began his presentation with the following introduction:

“In the last 40 years, since my first CMOS chip development in 5u SOS, I’ve watched the power density of silicon chips increase every generation, with higher switching frequencies and larger and larger currents making power integrity a serious design profession. For good reason, the two longest traces on opposite corners of a wire bonded DIP package just don’t seem like a good power delivery solution anymore. How can we help with that?  Glad you asked!”

Alan went on to discuss power management challenges in SoCs and chiplets. He covered topics such as the Analog Bits portfolio of on-die power management IP’s, the benefits of this IP, silicon results on TSMC N3E, and future work. He detailed several high-profile challenges being faced by many designers today. These include:

  • Power integrity and noise
  • Dynamic power management
  • Static voltage drop
  • Heterogeneous integration
  • Leakage power
  • Transient voltage spikes and voltage sags
  • Thermal hazards

He then detailed the various IPs available from Analog Bits to address the above challenges:

  • PVT Sensors – integrated and pin-less
  • Power On Reset and Over Current Detection Macro
  • Power Supply Glitch Detector
  • Power Supply Droop Detector
  • Low Dropout Regulator

The impact of a comprehensive library of IP like this can be substantial. Alan touched on some of that impact, including improved power efficiency, faster transient response and efficient regulation, enhanced reliability and improved yield, voltage scalability, integration and space savings, and noise reduction. Quite a list of improvements.

TSMC N3E Test Chip

He then went on to show several actual silicon results from TSMC’s N3E process. The response of the Droop Detector to a slow power slew was shown as well as the linearity of the system against a programmable input threshold. Results over temperature were presented that illustrated the stability and quality of the design. Performance of the PVT sensor was also shown over multiple conditions. The programmability of the Power On Reset macro was shown in detail as well.

Overall, an impressive portfolio of IP and an impressive set of results on an advanced process.

To Learn More

If you’d like to dig into the array of precision IPs offered by Analog Bits, you can do so here. And that’s how Analog Bits leads the way at TSMC OIP with high-accuracy sensors.


TSMC N3E is ready for designs, thanks to IP from Synopsys

TSMC N3E is ready for designs, thanks to IP from Synopsys
by Daniel Payne on 10-12-2023 at 10:00 am

synopsys ucie phy ip min

TSMC has been offering foundry services since 1987, and their first 3nm node was called N3 and debuted in 2022; now they have an enhanced 3nm node dubbed N3E that has launched.  Every new node then requires IP that is carefully designed, characterized and validated in silicon to ensure that the IP specifications are being met and can be safely used in SoC or multi-die system designs. This new IP must cover a wide range of functions, like interface, memory and logic. Synopsys has a large IP team that has risen to the challenge by creating new IP for the TSMC N3E node and achieving first-pass silicon success.

Chiplet Interconnect

Systems made up of heterogeneous chiplets require die-to-die communication, and that’s where the UCIe standard comes into play. Synopsys is a Contributor member of the UCIe Consortium, and they offer IP for both a UCIe Controller and a UCIe PHY in the TSMC N3E node.

The UCIe PHY IP had first silicon results in August 2023, showing data rates of 16Gbps and scalable to 24Gbps per channel. . Earlier this year, Intel unveiled world’s first Intel-Synopsys UCIe interoperability test chip demo at Intel Innovation. The interoperability was between Synopsys UCIe PHY IP on TSMC N3E process and Intel PHY IP on Intel 3 technology.

Industry’s Broadest Interface IP Portfolio on TSMC N3E

The IEEE approved the 802.3 standard for Ethernet back in 1983, quite the extended standard, while the Synopsys 224G Ethernet PHY IP had first silicon success in August 2023. Network engineers look at the eye diagram to see the 224Gbps PAM-4 encoding. Jitter levels surpassed both the IEEE 802.3 and OIF standard specifications.

Supporting standards like PCI Express 6.0, 400G/800G Ethernet, CCIX, CXL 2.0/3.0, JESD204 and CPRI there is the Synopsys Multi-Protocol 112G PHY IP. Engineers can combine this PHY IP with a MAC and PCS to build a 200G/400G/800G Ethernet block.

SDRAM and memory modules can use the Synopsys DDR5 PHY IP on TSMC N3E to achieve transfer rates up to 8400Mbps. You can see the wide open eye and clear margins for this IP operating at speed.

The PCI Express standard started out in 2003 and has been continually updated to meet the growing demands of cloud computing, storage, and AI. PCIe 5.0 is now supported using the Synopsys PCIe 5.0 PHY IP. First silicon on TSMC N3E showed operating speeds of 32 GT/s, and the Synopsys PCIe 5.0 PHY IP is listed on the PCI-SIG Integrators list.

I’ve been using USB-C on my MacBook Pro, iPad Pro and Android phone for years now. Synopsys now supports USB-C 3.2 and DisplayPort 1.4 PHY IP in the latest TSMC process. With this IP users can connect up to 8K Ultra High-Definition displays.

Smartphone companies standardized on the MIPI protocol years ago as an efficient way to connect cameras, and the Synopsys MIPI C-PHY IP/D-PHY IP can operate at 6.5Gb/s per lane and 6.5Gs/s per trio. The C-PHY IP supports v2.0, and the D-PHY IP2.1.

The latest Synchronous DRAM controller spec is LPDDR5X, supporting data transfer speeds up to 8533Mbps, a 33% improvement over LPDDR5 memory. The Synopsys LPDDR5X/5/4X Controller is silicon-proven, and ready to be designed with.

Logic Libraries and Memories

Up to half the area of an SoC can be memories, so the good news is that the Synopsys Foundation IP allows you to add memories and logic library cells quickly into a new design. Here are the test chip diagrams from Synopsys on the TSMC N3E node for memories and logic libraries.

Summary

TSMC and Synopsys have collaborated quite well together over the years, and that partnership now extends to the N3E node where SoC designers can find silicon-tested IP for interfaces, memories and logic. Power, performance and yield are looking attractive for N3E, so the technology is ready for your most demanding designs. Starting a design with N3E also provides you a quicker path to migrate to the N3P process.

Instead of creating all of your own IP from scratch, which will lengthen your schedule, require more engineering resources and increase risk, why not take a look at the proven and broad Synopsys IP portfolio for N3E .

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The True Power of the TSMC Ecosystem!

The True Power of the TSMC Ecosystem!
by Daniel Nenni on 10-02-2023 at 6:00 am

logo chart 092623

The 15th TSMC Open Innovation Platform® (OIP) was held last week. In preparation we did a podcast with one of the original members of the TSMC OIP team Dan Kochpatcharin. Dan and I talked about the early days before OIP when we did reference flows together. Around 20 years ago I did a career pivot and focused on Strategic Foundry Relationships. The importance of the foundries was clear to me and I wanted to be an integral part of that ecosystem. As it turns out it was a great career move, absolutely.

Before I get to the importance of the early TSMC reference flow days let’s talk about the recent OIP event. It was held at the Santa Clara Convention Center and it was a full house. For those other semiconductor event coordinators, if you want full semiconductor attendance use the Santa Clara Convention Center. Local hotels or the San Jose Convention Center are not convenient and convenience means attendance. TSMC switched to the Santa Clara Convention Center from San Jose a few years back and the rest as they say is history, TSMC hosts the best semiconductor networking events.

This year OIP was all about packaging and rightly so. It is the next foundry battleground and TSMC is once again building a massive ecosystem appropriately named the 3D Fabric Alliance:

TSMC Announces Breakthrough Set to Redefine the Future of 3D IC New 3Dblox 2.0 and 3DFabric Alliance Achievements Detailed at 2023 OIP Ecosystem Forum

“As the industry shifted toward embracing 3D IC and system-level innovation, the need for industry-wide collaboration has become even more essential than it was when we launched OIP 15 years ago,” said Dr. L.C. Lu, TSMC fellow and vice president of Design and Technology Platform. “As our sustained collaboration with OIP ecosystem partners continues to flourish, we’re enabling customers to harness TSMC’s leading process and 3DFabric technologies to reach an entirely new level of performance and power efficiency for the next-generation artificial intelligence (AI), high-performance computing (HPC), and mobile applications.”

L.C. Lu has been part of the TSMC OIP since the beginning, he worked for Dr. Cliff Hou. From 1997 to 2007 Cliff established the TSMC PDK and reference flow development organizations which then led to the OIP. Cliff Hou is now TSMC Senior Vice President, Europe & Asia Sales and Research & Development / Corporate Research.

L.C. updated us on the progress of the 3D Alliance and 3D Blox which is an incredible piece of technology that is open to all customers, partners and competitors alike. It is an industry standard in the making for sure. We covered 3D Blox HERE and TSMC gave us this update:

Introduced last year, the 3Dblox open standard aims to modularize and streamline 3D IC design solutions for the semiconductor industry. With contribution from the largest ecosystem of companies, 3Dblox has emerged as a critical design enabler of future 3D IC advancement.

The new 3Dblox 2.0, launched today, enables 3D architecture exploration with an innovative early design solution for power and thermal feasibility studiesThe designer can now, for the first time in the industry, put together power domain specifications and 3D physical constructs in a holistic environment and simulate power and thermal for the whole 3D system. 3Dblox 2.0 also supports chiplet design reuse features such as chiplet mirroring to further improve design productivity.

3Dblox 2.0 has won support from key EDA partners to develop design solutions that fully support all TSMC 3DFabric offerings. Those comprehensive design solutions provide designers with key insights to make early design decisions, accelerating design turnaround time from architecture to final implementation.

TSMC also launched the 3Dblox Committee, organized as an independent standard group, with the goal to create an industry-wide specification that enables system design with chiplets from any vendors. Working with key members including Ansys, Cadence, Siemens, and Synopsys, the committee has ten technical groups of different subjects and proposes enhancements to the specs and maintain the interoperability of EDA tools. Designers can now download the latest 3Dblox specifications from the 3dblox.org website and find more information about 3Dblox and its tool implementation by EDA partners.

Back to the reference flows, I was the Strategic Foundry Relationship Advisor for Solido Design Automation out of Saskatoon Canada and Berkeley Design Automation (BDA) in Silicon Valley at the time. Back then EDA included a lot of point tools inside the design flow since no one company could do it all. So all of the point tool companies looked to TSMC for guidance on how to interoperate inside a customer’s design flow. This was not only valuable experience, it provided much needed exposure for EDA start-ups to the TSMC customer base. In the case of Solido and BDA, it not only led to rapid adoption by TSMC’s top customers, TSMC itself licensed the tools for internal use which is the ultimate seal of approval. Solido and BDA were both acquired by Seimens EDA and their close relationships with TSMC was a big part of that transaction, believe it.

A similar process was developed for silicon proven IP. I am also a Foundry Relationships Advisor for IP companies and not only do we get access to TSMC’s top customers, TSMC allows access to PDKs and taught us how to silicon prove our products. Notice on the TSMC OIP partner list the biggest market segment is IP companies for these exact reasons. IP is a critical enabler for the foundry business and getting silicon right the first time is what OIP is all about.

Bottom line:  In the foundry business it’s all about collaboration and TSMC built this massive ecosystem from the ground up. Not only does it reduce customer risk of designing to new processes, the close collaboration between TSMC and the ecosystem partners multiplies the total annual ecosystem R&D investments exponentially.

Also Read:

TSMC’s First US Fab

The TSMC OIP Backstory

The TSMC Pivot that Changed the Semiconductor Industry!


TSMC’s First US Fab

TSMC’s First US Fab
by Daniel Nenni on 09-25-2023 at 6:00 am

WaferTech TSMC

TSMC originally brought the pure-play foundry business to the United States in 1996 through a joint venture with customers Altera, Analog Devices, ISSI, and private investors (no government money). Altera is now part of Intel but ADI is still a top TSMC customer and enthusiastic supporter. I have seen the ADI CEO Vincent Roche present at recent TSMC events and his TSMC partnership story is compelling. This joint venture was part of TSMC’s customer centric approach to business, responding directly to customer requests.

The WaferTech fab was established in Camas Washington (just North of the Oregon/Washington border) in 1996 with an investment of more than $1B which was a huge amount of money at the time. Production started two years later at .35 micron which was part of the Philips technology transfer that TSMC was founded upon. In 2000 TSMC bought out the partners and private investors, taking full control of the Washington fab. It is now called TSMC Fab 11 but clearly this fab was ahead of its time, absolutely.

From TSMC:

WaferTech focuses on Embedded Flash process technology while supporting a broad TSMC technology portfolio on line-widths ranging from 0.35-microns down to 0.16-microns. We specialize in helping companies deliver differentiated products and work with them on a number of customized and manufacturing “phase-in” projects. As a result, WaferTech delivers the latest generation semiconductors around the globe, supporting innovations in automotive, communications, computing, consumer, industrial, medical and military/aerospace applications.

To complement our world class process manufacturing services, WaferTech also provides test and analysis services at our Camas, Washington facility. Moreover, TSMC provides design, mask and a broad array of packaging and backend services at its other locations around the world. WaferTech also is a host for TSMC’s foundry-leading CyberShuttle™ prototyping services that help reduce overall design risks and production costs.

WaferTech, First U.S. Pure-play Foundry Ships Production Qualified Product ahead of Plan Issued by: Taiwan Semiconductor Manufacturing Company Ltd. Issued on: 1998/07/07

“With WaferTech on-line and shipping, TSMC customers gain another assured source for wafers produced to our standards of excellence,” said Ron Norris, president of TSMC, USA and a director of WaferTech. “Now TSMC is the only foundry in the world to transparently support customers from geographically dispersed sites.”

Ron Norris is another hire TSMC made with TI roots. Ron himself was a semiconductor legend. He started his career at TI and held executive level positions at Microchip in Arizona, Fairchild Semiconductor in Silicon Valley, and Data I/O Systems in Redmond WA, so he certainly knew the challenges of semiconductor manufacturing in the United States.

Historically, TSMC doesn’t just build fabs, TSMC builds communities. In fact, a TSMC fab itself is a community with everything you need to help maintain a work life balance. I have spent a lot of time in different fabs around the world but for the most part they were TSMC fabs in Taiwan. I still consider the Hsinchu Hotel Royal (walking distance from TSMC Fab 12A) as my second home. I remember flying in on my birthday one year and the staff had a mini birthday celebration when I arrived. Yes, they are that good, but I digress.

One thing you have to remember is that in Taiwan, working for TSMC brings status. You are a rockstar. Working for Samsung in South Korea has a similar aura. When TSMC breaks ground on a new fab location in Taiwan you can expect a whole support ecosystem to develop around it with everything a TSMC fab needs to be successful including housing and university level education for recruiting and employee growth.

Bottom line: Working for TSMC in Taiwan is like joining a very large and very successful family business.

Unfortunately, in Camas Washington, that was not the case. The WaferTech campus is a 23 acre complex housed on 260 acres. The main fabrication facility consists of a 130,000 square foot 200mm wafer fabrication plant.  Additional fabs were planned but never built, a support ecosystem never formed, thus the TSMC Taiwan fab recipe was called out as a failure in the US.

Many reasons have been sited for this “failure” including high costs, problems attracting local talent, and timing (soft economy), but in my opinion it also had a lot to do with the rockstar factor. In the US we had forgotten or did not know yet how important semiconductors were to modern life and TSMC was not a big name in the US like it is today.

Now that TSMC is building fabs in Arizona, Kumamoto Japan, and Dresden Germany it will be interesting to see how different the TSMC experience is in these world wide locations.

Also Read:

How Taiwan Saved the Semiconductor Industry

Morris Chang’s Journey to Taiwan and TSMC

How Philips Saved TSMC

The First TSMC CEO James E. Dykes

Former TSMC President Don Brooks

The TSMC Pivot that Changed the Semiconductor Industry!

The TSMC OIP Backstory


The TSMC OIP Backstory

The TSMC OIP Backstory
by Daniel Nenni on 09-18-2023 at 6:00 am

TSMC OIP 2023

This is the 15th anniversary of the TSMC Open Innovation Platform (OIP). The OIP Ecosystem Forum will kick off on September 27th in Santa Clara, California and continue around the world for the next two months in person and on-line in North America, Europe, China, Japan, Taiwan, and Israel. These are THE most attended semiconductor ecosystem networking events! I hope to see you there!

For more information check TSMC.com.

Growing up in Silicon Valley with a 40 year career in the semiconductor industry/ecosystem has been an amazing experience. Working with the most intelligent people around the world, solving some of the most complex problems, and seeing the fruits of our labor change the world, there is nothing like being a semiconductor professional.

This next passage is an updated chapter from our book “Fabless: The transformation of the Semiconductor Industry“. It captures the OIP backstory quite nicely but there is just one thing I would like to add. The amount of money invested by TSMC and the OIP partners in the ecosystem every year is billions of dollars. The total ecosystem investment is most certainly more than a trillion dollars and I must say we certainly are getting our money’s worth, absolutely.

In Their Own Words: TSMC and Open Innovation Platform
TSMC, the largest and most influential pure-play foundry,
has many fascinating stories to tell. In this section, TSMC
covers some of their basic history, and explains how creating
an ecosystem of partners has been key to their success, and to
the growth of the semiconductor industry.

The history of TSMC and its Open Innovation Platform (OIP)® is, like almost everything in semiconductors, driven by the economics of semiconductor manufacturing. Of course, ICs started 50 years ago at Fairchild, very close to where Google is headquartered today (these things go in circles). The planarization approach, whereby a wafer (just 1” originally) went through each process step as a whole, led to mass production. Other companies such as Intel, National, Texas Instruments and AMD soon followed and started the era of the Integrated Device Manufacturer (although we didn’t call them that back then, we just called them semiconductor companies).

The next step was the invention of ASICs with LSI Logic and VLSI Technology as the pioneers. This was the first step of separating design from manufacturing. Although the physical design was still done by the semiconductor company, the concept was executed by the system company. Perhaps the most important aspect of this change was not that part of the design was done at the system company, but rather the idea for the design and the responsibility for using it to build a successful business rested with the system company, whereas IDMs still had the “if we build it they will come” approach, with a catalog of standard parts.

In 1987, TSMC was founded and the separation between manufacture and design was complete. One missing piece of the puzzle was good physical design tools. Fortunately, Cadence was created in 1988 from the merger of SDA and ECAD (and soon after, Tangent). Cadence was the only supplier of design tools for physical place and route at the time. It was now possible for a system company to buy design tools, design their own chip and have TSMC manufacture it. The system company was completely responsible for the concept, the design, and selling the end-product (either the chip itself or a system containing it). TSMC was completely responsible for the manufacturing (usually including test, packaging and logistics too).

At the time, the interface between the foundry and the design group was fairly simple. The foundry would produce design rules and SPICE parameters for the designers; the design would be given back to the foundry as a GDSII file and a test program. Basic standard cells were required, and these were available on the open market from companies like Artisan, or some groups would design their own. Eventually TSMC would supply standard cells, either designed in-house or from Artisan or other library vendors (bearing an underlining royalty model transparent to end users). However, as manufacturing complexity grew, the gap between manufacturing and design grew too. This caused a big problem for TSMC: there was a lag from when TSMC wanted to get designs into high volume manufacturing and when the design groups were ready to tape out. Since a huge part of the cost of a fab is depreciation on the building and the equipment, which is largely fixed, this was a problem that needed to be addressed.

At 65 nm TSMC started the Open Innovation Platform (OIP) program. It began at a relatively small scale but from 65 nm to 40 nm to 28 nm the amount of manpower involved went up by a factor of 7. By 16 nm FinFET, half of the design effort is IP qualification and physical design because IP is used so extensively in modern SoCs. OIP actively collaborated with EDA and IP vendors early in the life-cycle of each process to ensure that design flows and critical IP were ready early. In this way, designs would tape-out just in time as the fab was starting to ramp so that the demand for wafers was well-matched with the supply.

In some ways the industry has gone a full circle, with the foundry and the design ecosystem together operating as a virtual IDM. The existence of TSMC’s OIP program further sped up disaggregation of the semiconductor supply chain. This was enabled partly by the existence of a healthy EDA industry and an increasingly healthy IP industry. As chip designs had grown more complex and entered the SoC era, the amount of IP on each chip was beyond the capability or the desire of each design group to create. But, especially in a new process, EDA and IP qualification was a problem.

On the EDA side, each new process came with some new discontinuous requirements that required more than just expanding the capacity and speed of the tools to keep up with increasing design size. Strained silicon, high-K metal gate, double patterning and FinFETs each require new support in the tools and designs to drive the development and test of the innovative technology.

On the IP side, design groups increasingly wanted to focus all their efforts on parts of their chip that differentiated them from their competition, and not on re-designing standard interfaces. But that meant that IP companies needed to create the standard interfaces and have them validated in silicon much earlier than before.

The result of OIP has been to create an ecosystem of EDA and IP companies, along with TSMC’s manufacturing, to speed up innovation everywhere. Because EDA and IP groups need to start work before everything about the process is ready and stable, the OIP ecosystem requires a high level of cooperation and trust.

When TSMC was founded in 1987, it really created two industries. The first, obviously, is the foundry industry that TSMC pioneered before others entered. The second was the fabless semiconductor industry where companies did not need to invest in fabs.

The foundry/fabless model largely replaced IDMs and ASIC. An ecosystem of co-operating specialist companies innovates fast. The old model of having process, design tools and IP all integrated under one roof has largely disappeared, along with the “not invented here” syndrome that slowed progress since ideas from outside the IDMs had a tough time penetrating. Even some of the earliest IDMs from the “Real men have fabs” era have gone “fab lite” and use foundries for some of their capacity, typically at the most advanced nodes.

Legendary TSMC Chairman Morris Chang’s “Grand Alliance” is a business model innovation of which OIP is an important part, gathering all the significant players together to support customers—not just EDA and IP, but also equipment and materials suppliers, especially for high-end lithography.

Digging down another level into OIP, there are several important components that allow TSMC to coordinate the design ecosystem for their customers.

  • EDA: the commercial design tool business flourished when designs got too large for hand-crafted approaches and most semiconductor companies realized they did not have the expertise or resources in-house to develop all their own tools. This was driven more strongly in the front-end with the invention of ASIC, especially gate-arrays, and then in the back end with the invention of foundries.
  • IP: this used to be a niche business with a mixed reputation, but now is very important with companies like ARM, Imagination, CEVA, Cadence, and Synopsys, all carrying portfolios of important IP such as microprocessors, DDRx, Ethernet, flash memory and so on. In fact, large SoCs now contain over 50% and sometimes as much as 80%.
  • Services: design services and other value-chain services calibrated with TSMC process technology helps customers maximize efficiency and profit, getting designs into high volume production rapidly.
  • Packaging: TSMC expanded the OIP ecosystem to include a 3D Fabric Alliance.
  • People: More than 3,000 TSMC employees are part of OIP plus 10,000 people from the more than 100 OIP partners. The OIP now includes 50,000 titles, 43,000 tech files, and 2,800 PDKs.

Processes are continuing to get more advanced and complex, and the size of a fab that is economical also continues to increase. This means that collaboration needs to increase as the only way to both keep costs in check and ensure that all the pieces required for a successful design are ready just when they are needed.

TSMC has been building an increasingly rich ecosystem for over 30 years and feedback from partners is that they see benefits sooner and more consistently than when dealing with other foundries. Success comes from integrating usage, business models, technology and the OIP ecosystem so that everyone succeeds. There are a lot of moving parts that all have to be ready. It is not possible to design a modern SoC without design tools. More and more SoCs involve more and more 3rd party IP, and, at the heart of it all, the process and the manufacturing ramp with its associated yield learning all needs to be in place at TSMC.

Bottom line: The OIP ecosystem has been a key pillar in enabling this sea of change in the semiconductor industry.

Also Read:

How Taiwan Saved the Semiconductor Industry

Morris Chang’s Journey to Taiwan and TSMC

How Philips Saved TSMC

The First TSMC CEO James E. Dykes

Former TSMC President Don Brooks

The TSMC Pivot that Changed the Semiconductor Industry!


The TSMC Pivot that Changed the Semiconductor Industry!

The TSMC Pivot that Changed the Semiconductor Industry!
by Daniel Nenni on 09-11-2023 at 6:00 am

Don Brooks Interview 2000

During my research I found an interview with Don Brooks from February 2000. It was very interesting and confirmed some of the things I knew about Don and brought up a few things I did not know. It’s an hour but it is a video of Don telling his story and is definitely worth a look. One of the things that was not mentioned however is the pivot that TSMC made when Don was president that enabled the transformation of the fabless semiconductor ecosystem, absolutely.

https://exhibits.stanford.edu/silicongenesis/catalog/cj789gh7170

Here are notes from the interview:

Don Brooks, former Senior Vice President of Texas Instruments and President and CEO of Fairchild Industries, discusses his experiences in semiconductor manufacturing.

00:00:00 Interviewer introduces Brooks and his overall career.

00:01:00 Discussion of going to school at SMU in a co-op program with Texas Instruments (TI), and his experience working in fabs (semiconductor fabrication plant) and with Jack Kilby.

00:05:10 Discusses TI’s attempt to vertically integrate while horizontally expanding the product line, and Intel’s departure from the DRAM business.

00:11:06 Discusses management at TI and leaving Texas Instruments to be President at Fairchild.

00:15:37 Discusses the demise of Fairchild, sale to Schlumberger, subsequent sale to National, and the Fujitsu proposed merger.

00:27:28 Discusses his upbringing and how he came to work at TI.

00:31:35 Discusses his work in venture capital, becoming the President of Taiwan Semiconductor Manufacturing Company (TSMC), and the context for foundry business and product engineering in the semiconductor industry.

00:37:35 Discusses Morris Chang, the politics of being president at TSMC, and Europe, the U.S., and Taiwan’s cultural differences in the semiconductor industry.

00:47:15 Discussion of the lifetime of fabs, the cost of equipment, and profit sharing.

00:57:20 Discusses moving back to the US, working at UMC on the Board of Directors, and focusing on his work in venture capital.

Interviewed by Rob Walker, February 8, 2000, Sunnyvale, California.

In regards to the pivot, this is what I remember but it is open for debate. Back when TSMC first started it was a very difficult transition from using an ASIC company like VLSI Technology or LSI Logic to using a pure-play foundry. There was a serious amount of foundation IP, PDKs and customer owned tooling (COT) that had to be done before a fabless company could design to a new process.

When TSMC first arrived a pureplay foundry was a very difficult sell to chip designers since there was no real ecosystem to support them. IDMs were the first targets since they had internal EDA and IP groups but the bigger margin markets were the emerging fabless companies or what was to be the Qualcomm, Nvidia, and Broadcoms of the world.

The first couple of processes TSMC used were licensed from Philips so there were some PDKs and IP available. After that TSMC developed their own processes with “greenfield” fabs and the real work began.

Not long after assessing the TSMC sales strategy, Don Brooks sold the TSMC board on the idea of opening up TSMC’s design rules to the EDA and IP companies for quicker and broader adoption of the TSMC process technologies. I don’t recall exactly the first set of design rules TSMC released,  I believe it was 1.0µm, but I do recall the first commercial EDA/IP company to adopt them and it was Compass Design Automation, a spin out of VLSI Technology, which was later purchased by Avant! (I worked for Avant!). In fact, my god friend and favorite co-author Paul McLellan, a long time VLSI Technology employee, was president of Compass.

To make a long story short, not only did all of the EDA and IP companies adopt TSMC PDKs, TSMC’s competitors did as well. A fabless company could design a chip for TSMC and take it to UMC, Chartered (now GF), or SMIC for second source manufacturing. I experienced this first hand many times.  One tape-out I was involved in originated at TSMC and was manufactured by all four foundries during its lifetime. This “T like” process development strategy continued until the FinFET era (16nm). The PDK “accessibility” made TSMC what they are today, the highest margin foundry the world has ever seen. But during the CMOS years (down to 28nm) TSMC’s margins were compressed by the smaller foundries so this level of openness was a double edged sword.

The bottom line: Morris Chang’s hands-off management style during Don’s tenure was a good thing. Had Don Brooks not opened up the TSMC design rules the semiconductor ecosystem may not be what it is today, a true force of nature.

Also Read:

Former TSMC President Don Brooks

The First TSMC CEO James E. Dykes

How Philips Saved TSMC

Morris Chang’s Journey to Taiwan and TSMC

How Taiwan Saved the Semiconductor Industry


Former TSMC President Don Brooks

Former TSMC President Don Brooks
by Daniel Nenni on 09-04-2023 at 6:00 am

Don Brooks

Don Brooks is well known to many long time semiconductor insiders, like myself, but most SemiWiki readers have probably never heard of him. Don is a semiconductor legend and here is his story. This will be in two parts since he had a big impact on the semiconductor industry and TSMC. From 1991 to 1997 Don served as President of TSMC and helped grow the nascent company into what it is today, the world’s largest semiconductor foundry with a market capitalization of $500B.

Don Brooks passed away in 2013 and here is the story from his memorial. If you read between the lines you can get a real sense of who Don really was, a very intelligent, driven, semiconductor professional of the highest caliber, absolutely.

Don graduated from Sunset High School in 1957 and was a key player on their basketball team, which won the City Championship his senior year. Don attended Tarleton State College on a basketball scholarship his freshman year. He married his high school sweetheart in 1958 and enrolled in SMU under a co-op program with Texas Instruments.

He happened to be assigned to TI’s Research Lab during a time when Jack Kilby invented/developed the integrated circuit. Consequently, his entire 25-year career at TI focused on the commercialization and production of semiconductors. He rapidly rose through the ranks of TI’s management and became the youngest man ever to be promoted to Senior Vice President at Texas Instruments. Under his leadership TI developed a reputation as the world’s leading supplier of MOS memories.

In 1983 he became President & CEO of Fairchild Industries in Mountain View, CA. He founded KLM Capital in 1988 and served as its Chairman for years. Don joined TSMC as President in 1991. During his tenure as President, TSMC returned to profitability, and grew to become the world’s largest independent semiconductor fabrication company.

Morris Chang, Founder and Chairman of TSMC had these words to say about Don’s tenure as President of the Company “Since his arrival in 1991 Don Brooks has provided dramatic leadership that built TSMC into the world’s most successful dedicated foundry”. TSMC grew at an average annual rate of 54% over Don’s time as President of the Company and achieved record profits.

Following TSMC, he was a board member of United Microelectronics Corporation of Taiwan (NYSE: UMC and TSE: 2303) and previously served as its President and co-Chief Executive Officer from 1997-1999. From what I understand, Morris Chang and Don had a disagreement (broken promise) and moving across the street to UMC was Don’s way of resolving it.

In addition to Don’s success as a senior executive, he also had significant success as a private investor including, but not limited to;

Don was the first outside investor in Silicon Labs (SLAB; NASDAQ) one of the premier success stories of the Austin high tech boom, and he was the first outside investor in Broadcom (BRCM; NASDAQ) one of the most successful startup semiconductor companies of all time.

One thing that impresses me about Don and other semiconductor legends is their dedication to family. In my opinion, fifty plus year marriages show true character, compassion, and the ability to compromise. My father’s parents were married for 72 years, I saw it first hand, something I aspire to.

There is a lot more to Don’s TSMC story of course and that is what I will cover in Part II.

Also Read:

How Taiwan Saved the Semiconductor Industry

Morris Chang’s Journey to Taiwan and TSMC

How Philips Saved TSMC

The First TSMC CEO James E. Dykes


Arm Inches Up the Infrastructure Value Chain

Arm Inches Up the Infrastructure Value Chain
by Bernard Murphy on 08-30-2023 at 6:00 am

Arm just revealed at HotChips their compute subsystems (CSS) direction led by CSS N2. The intent behind CSS is to provide pre-integrated, optimized and validated subsystems to accelerate time to market for infrastructure system builders. Think HPC servers, wireless infrastructure, big edge systems for industry, city, enterprise automation. This for me answers how Arm can add more value to system developers without becoming a chip company. They know their technology better than anyone else; by providing pre-designed, optimized and validated subsytems – cores, coherent interconnect, interrupt, memory management and I/O interfaces, together with SystemReady validation – they can chop a big chunk out of the total system development cycle.

Accelerating Custom Silicon

A completely custom design around core, interconnect, and other IPs obviously provides maximum flexibility and ability to differentiate but at a cost. That cost isn’t only in development but also in time to deployment. Time is becoming a very critical factor in fast moving markets – just look at AI and the changes it is driving in hyperscaler datacenters. I have to believe current economic uncertainties compound these concerns.

Those pressures are likely forcing an emphasis on differentiating only where essential and standardizing everywhere else, especially when proven experts can take care of a big core component. CSS provides a very standard yet configurable subsystem for many-core compute, include N2 cores (in this case), the coherent mesh network between those cores, together with interrupt and memory management, cache hierarchy, chiplet support through UCIe or custom interfaces, DDR5/LPDDR5 external memory interface, PCIe/CXL Gen5 for fast IO and or coherent IO, expansion IO, and system management.

All PPA optimized for an advanced 5nm TSMC process and proven SystemReady® with a reference software stack. The system developer still has plenty of scope for differentiation through added accelerators, specialized compute, their own power management, etc.

Neoverse V2

Arm also announced a next step in the Neoverse V-series, unsurprisingly improved over the V1 version with improved integer performance and reduction in system level cache misses. There is improvement on a variety of other benchmarks also.

Also noteworthy is its performance in the NVIDIA Grace-Hopper combo (based on Neoverse V2). NVIDIA shared real hardware data with Arm on performance versus Intel Sapphire Rapids and AMD Genoa. In raw performance the Grace CPU was mostly at par with AMD and generally faster than Sapphire Rapids by 30-40%.

Most striking for me was their calculation for a datacenter limited to 5MW, important because all datacenters are ultimately power limited. In this case Grace bested AMD in performance by between 70% and 150% and was far ahead of Intel.

Net value

First on Neoverse’s contribution to Grace-Hopper – wow. That system is at the center of the tech universe right now, thanks to AI in general and large language models in particular. This is an incredible reference. Second, while I’m sure that Intel and AMD can deliver better peak performance than Arm-based systems, and Grace-Hopper workloads are somewhat specialized, (a) most workloads don’t need high end performance and (b) AI is getting into everything now. It is becoming increasingly difficult to make a case that, for cost and sustainability over a complete datacenter, Arm-based systems shouldn’t play a much bigger role especially as expense budgets tighten.

For CSS-N2, based on their own analysis Arm estimates up to 80 engineering years of effort required to develop the CSS N2 level of integration, a number that existing customers confirm is in the right ballpark. In an engineer-constrained environment, this is 80 engineering years they can drop from their program cost and schedule without compromising whatever secret differentiation the want to add around the compute core.

These look like very logical next steps for Arm in their Neoverse product line. Faster performance in the V-series and let customers take advantage of Arm’s own experience and expertise in building N2-based compute systems, while leaving open lots of room for adding their own special sauce. You can read the press release HERE.