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All in One Bluetooth Audio: A Complete Solution on a TSMC 12nm Single Die

All in One Bluetooth Audio: A Complete Solution on a TSMC 12nm Single Die
by Daniel Nenni on 04-27-2026 at 6:00 am
Categories: Ceva, Events, IP, Semiconductor, TSMC

All in One Bluetooth Audio A Complete Solution on a TSMC 12nm Single Die

The rapid evolution of wireless audio has placed unprecedented demands on system integration, power efficiency, and performance. Against this backdrop, the webinar “All-in-One Bluetooth Audio: A Complete Solution on a TSMC 12nm Single Die” offers a timely and technically rich exploration of how modern semiconductor design is meeting these challenges. For engineers, architects, and product leaders working in wireless audio, connectivity, or system-on-chip (SoC) design, this session provides both practical insights and a forward-looking perspective on integration trends shaping the industry.

REGISTER HERE

At the heart of the webinar is a detailed examination of a fully integrated Bluetooth audio solution implemented on a single die using advanced 12nm process technology from TSMC. Moving to a single-die architecture represents a significant shift from traditional multi-chip or module-based designs. By consolidating RF front-end, baseband processing, digital signal processing (DSP), memory, and power management into one silicon platform, designers can achieve tighter coupling between subsystems, reduced latency, and improved energy efficiency. This level of integration is particularly critical for applications such as true wireless earbuds, smart headsets, and embedded audio systems, where size, battery life, and performance must be optimized simultaneously.

One of the key reasons to attend this webinar is the opportunity to understand the architectural trade-offs involved in such high levels of integration. Designing on a 12nm node introduces both opportunities and constraints. While the process enables higher transistor density and lower power consumption, it also requires careful attention to analog/RF performance, noise isolation, and thermal considerations. The session is expected to walk through these challenges, offering insights into how designers balance digital scaling benefits with the sensitivities of RF and mixed-signal blocks.

Another compelling aspect of the webinar is its focus on system-level optimization. Bluetooth audio is no longer just about connectivity; it is about delivering high-quality, low-latency audio experiences under strict power budgets. Attendees will gain visibility into how DSP pipelines are structured for efficient audio processing, how coexistence mechanisms are implemented to handle interference, and how power management strategies are designed to extend battery life without compromising performance. These are not abstract concepts but practical considerations that directly impact product success in competitive consumer markets.

The webinar also promises to cover silicon validation and real-world performance metrics. This is particularly valuable because it bridges the gap between theoretical design and deployed systems. Understanding how a single-die solution performs in terms of power consumption, latency, RF robustness, and audio fidelity provides attendees with a benchmark for their own designs. It also offers a clearer picture of what is achievable with current process technology and integration techniques.

Beyond the technical depth, the webinar is relevant because it reflects a broader industry trend toward consolidation and platformization. As wireless audio devices become more ubiquitous, the ability to deliver complete, scalable solutions on a single chip is becoming a competitive differentiator. Engineers who understand these trends will be better positioned to design future-proof systems and make informed decisions about architecture, process nodes, and integration strategies.

Finally, attending this webinar is an efficient way to stay current in a fast-moving field. Instead of piecing together information from disparate sources, participants can gain a cohesive understanding of end-to-end Bluetooth audio system design in a single session. Whether you are an RF engineer looking to understand digital integration impacts, a DSP developer interested in system constraints, or a product engineer evaluating design trade-offs, the content is directly applicable to real-world challenges.

REGISTER HERE

Bottom line: This webinar is more than a product overview; it is a deep technical dive into the future of integrated wireless audio systems. By attending, you gain not only knowledge of a specific implementation but also a framework for thinking about integration, efficiency, and performance in next-generation designs.

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From Satellites to 5G: Ceva’s PentaG-NTN™ Lowers Barriers for Terminal Innovators

Ceva IP: Powering the Era of Physical AI

Ceva Wi-Fi 6 and Bluetooth IPs Power Renesas’ First Combo MCUs for IoT and Connected Home

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Carbon in the Age of AI Chips: What the Semiconductor Industry Needs to Know This Earth Day

Carbon in the Age of AI Chips: What the Semiconductor Industry Needs to Know This Earth Day
by Admin on 04-23-2026 at 6:00 am
Categories: Semiconductor Services, TechInsights, TSMC

Carbon in the Age of AI Chips

Stephen Russell: Senior Technical Fellow, TechInsights

Every April, Earth Day prompts a flurry of corporate sustainability pledges and green-tinted press releases. But for the semiconductor industry in 2026, the conversation has moved well past pledges. Carbon accountability is now a procurement requirement, a regulatory expectation, and increasingly a design constraint. This Earth Day, TechInsights is releasing a new sustainability report, Carbon in the Age of AI Chips. Authored by TechInsights Senior Technical Fellow Stephen Russell and Senior Sustainability Analyst Lara Chamness, the report examines where semiconductor emissions are actually coming from, why AI is accelerating the problem faster than most reporting methods can track, and what engineering, procurement, and sustainability teams can do about it right now.

Here’s a preview of what’s inside:

The Scale of the Problem Is Getting Harder to Ignore

Start with the headline numbers. Fabrication emissions are projected to reach 186 million metric tons of CO₂e in 2026, a record high, rising to approximately 247 million metric tons by 2030. Leading-edge technologies below 4nm will account for 26% of total emissions this year, climbing to 42% by 2030. Those are not abstract figures. They represent real consequences of real decisions: which fab to use, which memory configuration to specify, which supplier to source from.

What makes 2026 feel genuinely different from prior years is the convergence of three forces pushing carbon upstream into product decisions. Advanced manufacturing keeps getting more energy- and resource-intensive, especially at leading-edge logic and high-layer 3D NAND. AI demand is driving unprecedented silicon and memory intensity per system, not just more units but fundamentally heavier systems. And procurement teams are being asked, with increasing urgency, to defend supplier choices with traceable carbon logic rather than slide-deck narratives.

Manufacturing Carbon Is a Strategic Variable, Not a Fixed Cost

One of the report’s central arguments is that manufacturing carbon should not be treated as a black box or a rounding error. It is a strategic variable, and it responds to specific decisions.

The report’s Sustainability Matrix maps carbon hotspots across device types and toolsets. For advanced logic nodes, Scope 2 emissions driven by electricity are concentrated in lithography. For 3D NAND, dry etch can account for nearly half of total manufacturing emissions, driven by high-power plasma processes and high global warming potential gases. Some of those gases carry a 100-year GWP of around 25,000 times that of CO₂.

Perhaps the most striking case study involves backside power delivery (BSPD), a major scaling innovation that many assume carries a straightforward carbon penalty due to added process complexity. The reality is more nuanced. In an illustrative comparison of Intel 18A manufactured in the United States versus TSMC N2 manufactured in Taiwan, the Intel process results in lower manufacturing CO₂e per die. Not because it is simpler, but because the U.S. grid is cleaner. The electricity mix where a chip is fabricated can outweigh the complexity of the manufacturing process itself. That is a finding with immediate implications for anyone making sourcing or fab-selection decisions.

AI Hardware Is Scaling Emissions Faster Than Shipments

The report’s treatment of AI accelerators is where the numbers become genuinely striking. TechInsights’ Global AI GPU Manufacturing Carbon Emissions Forecast shows that by 2030, manufacturing emissions from AI GPU production are projected to rise more than twelvefold, from approximately 1.8 million metric tons CO₂e in 2024 to 21.6 million metric tons CO₂e. AI GPU manufacturing is expected to account for roughly 8.7% of total semiconductor die fabrication emissions by 2030. The average accelerator is expected to exceed one metric ton of CO₂e per unit by 2029.

The driver is not primarily bigger logic dies. It is memory, specifically high-bandwidth memory (HBM). The average AI accelerator is expected to integrate roughly 250 HBM dies by 2030. NVIDIA’s Rubin Ultra-class designs are projected to approach approximately 1 TB of HBM through higher stack counts and heights. As Stephen Russell notes, the AI-driven surge in HBM and advanced memory is likely to raise semiconductor manufacturing emissions in absolute terms, increasing memory wafer starts and adding process complexity even as leading manufacturers improve efficiency per transistor.

There is a subtler dimension the report explores carefully: yield. Stacking dies compounds yield loss, and in tall-stack HBM scenarios, stacking yields above 93% are necessary to prevent emissions per usable stack from rising sharply. That makes yield learning and process control first-order sustainability levers, not just cost levers.

The Client Device Story: Carbon Paid Upfront

The report’s third major focus is consumer and enterprise devices, where on-device AI is often framed as an operational efficiency win. Fewer cloud calls, lower network load, specialized local hardware: all genuine benefits. But the manufacturing emissions for those devices are paid upfront, and they are concentrated in places that might surprise you.

Using teardown-based analysis of AI PCs including recent Microsoft Surface and ASUS Zenbook models, the report finds a consistent pattern: memory and storage, not the headline processor or NPU, account for the majority of embodied carbon in AI PC platforms. Across the examples evaluated, memory accounts for roughly 43% to 57% of packaged-IC CO₂e, while the applications processor accounts for only about 14% to 21%.

The supplier concentration finding is particularly actionable. In one Surface Laptop 7 configuration, three suppliers account for approximately 73% of packaged-IC carbon. In a Zenbook S14 model, three suppliers account for roughly 84%. A small number of parts and vendors determine most of the footprint, which means platform configuration and supplier selection are among the highest-leverage carbon choices a product team can make.

What Can Actually Be Done

The report identifies a clear set of high-leverage actions: pursuing cleaner electricity and power purchase agreements, reducing yield loss and rework especially late in the flow and in stacked memory, substituting low-GWP gases with higher abatement efficiency, improving tool energy and utilization, and optimizing bit density and platform configuration.

Semiconductor sustainability has become a decision problem. The highest-impact choices around fab location, memory configuration, supplier mix, and platform architecture are made before a product ships, carrying carbon consequences that most legacy reporting methods cannot capture. The full report, Carbon in the Age of AI Chips, is available now.

LINK: Carbon in the Age of AI Chips | Earth Day eBook | TechInsights

Stephen Russell: Senior Technical Fellow

As Senior Technical Fellow for Sustainability at TechInsights, Stephen provides expert insight into carbon footprint across the entire technology life cycle, from raw materials through product manufacturing, use and end of life. Stephen also works on unique initiatives to characterize Scope 3 emissions in the use phase of consumer electronics products, with further reaching implications for data center and automotive applications.

Stephen is internationally recognized for technical research contributions and collaborations. These include being awarded best paper 2018 for the IEEE Journal Transactions on Power Electronics paper “High Temperature Electrical and Thermal Aging Performance and Application Considerations for SiC power DMOSFETs”. He led an exploratory research project in gallium oxide for power devices, presenting findings to the Royal Institution, London. While working in industry, he led the development of a new silicon IGBT product line and instigated a research and development project to use silicon carbide JFETs in circuit protection applications.

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TSMC Technology Symposium 2026 Overview

TSMC Technology Symposium 2026 Overview
by Daniel Nenni on 04-22-2026 at 12:00 pm
Categories: Events, Semiconductor, TSMC
2 Comments

Semiconductor Revenue $1T Accelleration

Yes, it is that time of year again, the 2026 TSMC Technology Symposium kick-off event in Silicon Valley. TSMC has never been in a better position to forecast the future of semiconductor technology and the industry itself. TSMC closely collaborates with the top semiconductor companies around the world and the top players in the semiconductor ecosystem. Never in the history of TSMC have they been in such a prominent position and the information that comes from that is astounding.

Dr. Kevin Zhang, Senior Vice President and Deputy Co-COO, again honored us with a press briefing before the event which is what we are talking about today. Next week we will talk in more detail about the event itself and some of the announcements. Unlike most of the media I will be there live with SemiWiki blogger Kalar Rajendiran.

Again, this is TSMC’s perspective on the semiconductor industry but it is backed collectively by the entire semiconductor ecosystem, absolutely.

The semiconductor industry is entering a new phase of accelerated growth and architectural transformation, driven primarily by artificial intelligence (AI) and high-performance computing (HPC). Recent projections indicate that semiconductor market growth has significantly outpaced earlier expectations, rising from a forecasted 10% to an actual 23% annual increase, with future projections reaching approximately 45% growth . This rapid expansion is largely attributed to AI-driven demand, which is reshaping both technology development and system-level design.

Could this be the first year that the semiconductor industry outpaces TSMC? Hard to believe but yes. TSMC revenue is expected by me to grow 30-40%. Here is the hitch: While wafer pricing is stable chip pricing is not. The bulk of the 45% revenue growth is due to chip pricing versus chip unit sales. Memory pricing is a big part of this but some of the AI chips (NVIDIA) are also selling at a premium.

A major milestone in this transformation is the advancement of global semiconductor revenue toward the $1 trillion mark, now expected to be achieved earlier than previously projected. As illustrated in the industry trend chart, AI represents the latest inflection point following previous computing waves such as PCs, the internet, and smartphones. By 2030, the semiconductor market is expected to exceed $1.5 trillion, with HPC and AI contributing over 55% of total demand, far surpassing other segments like smartphones (20%), automotive (10%), and IoT (10%) .

At the core of this growth is continuous innovation in semiconductor process technology. The roadmap for advanced nodes demonstrates a steady progression from nanometer-scale fabrication toward angstrom-class technologies. Nodes such as TSMC N2 and its enhanced derivative TSMC N2U focus on improving power, performance, and area (PPA) through design-technology co-optimization (DTCO). According to the technical data presented, N2U offers a 3–4% speed improvement at constant power, up to 10% power reduction at the same speed, and a modest increase in logic density. These incremental improvements are critical for maximizing return on investment for chip designers while maintaining compatibility with previous node designs.

Further advancements are seen in next-generation nodes such as A13, which extend technology leadership through optical shrink techniques. A 97% optical shrink enables approximately 6% area reduction while preserving backward compatibility in design rules. This allows designers to benefit from improved density without requiring extensive redesign, thereby accelerating product deployment.

While transistor scaling remains important, it is no longer sufficient to meet the exponential demands of AI workloads. Consequently, advanced packaging and system integration technologies have become central to performance scaling. Technologies such as CoWoS (Chip-on-Wafer-on-Substrate) and SoIC (System-on-Integrated-Chips) enable heterogeneous integration of logic and memory components. The HPC platform diagram illustrates how advanced logic dies, high-bandwidth memory (HBM), and photonic components are integrated into a single package to maximize compute density and efficiency.

The scaling of interposer size is a key enabler of this integration.  Interposer capacity is expanding from 3.3 reticle sizes to over 14 reticles by 2029, supporting up to 24 HBM stacks. This expansion allows for massive increases in memory bandwidth and compute capability. Additionally, wafer-scale integration technologies such as System-on-Wafer (SoW) extend this concept further, enabling integration at scales exceeding 40 reticles, equivalent to 64 HBM stacks.

Three-dimensional stacking technologies also play a critical role in enhancing interconnect density and power efficiency. SoIC technology enables vertical integration with significantly higher interconnect density—up to 56× compared to traditional 2.5D approaches—and improved power efficiency. This shift from planar to vertical integration reflects a broader industry trend toward system-level optimization rather than purely transistor-level scaling.

The impact of these innovations is evident in system-level performance metrics. The number of compute transistors within a single CoWoS package is projected to increase by up to 48× between 2024 and 2029. Similarly, memory bandwidth is expected to scale by 34× during the same period, driven by advancements in HBM technology and integration techniques.

Another critical innovation is the adoption of co-packaged optics (CPO) for high-speed interconnects. Traditional electrical interconnects face limitations in power efficiency and latency. By integrating optical communication directly into the package, systems can achieve up to 10× improvements in power efficiency and 20× reductions in latency, as shown in a performance comparison chart. This transition from electrical to optical signaling is essential for scaling AI infrastructure, where massive data movement between compute units is required.

Beyond data centers, semiconductor advancements are also enabling the emergence of physical AI applications, particularly in automotive and robotics. Modern vehicles are evolving into compute-centric platforms with significantly increased silicon content, incorporating advanced processors, sensors, and connectivity modules. Looking forward, humanoid robots represent a convergence of digital AI and physical interaction, requiring integrated systems for sensing, computation, motion control, and power management.

Bottom line: The semiconductor industry is transitioning from traditional scaling paradigms to a holistic, system-level approach that integrates advanced process nodes, heterogeneous packaging, photonics, and AI-driven architectures. This convergence is enabling unprecedented growth in computational capability and will define the technological landscape of the next decade.

Also Read:

TSMC to Elon Musk: There are no Shortcuts in Building Fabs!

TSMC Technology Symposium 2026: Advancing the Future of Semiconductor Innovation

Global 2nm Supply Crunch: TSMC Leads as Intel 18A, Samsung, and Rapidus Race to Compete

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TSMC to Elon Musk: There are no Shortcuts in Building Fabs!

TSMC to Elon Musk: There are no Shortcuts in Building Fabs!
by Daniel Nenni on 04-17-2026 at 10:00 am
Categories: Semiconductor, TSMC
1 Comment

Elon Musk Terafab 2026

The opening of the TSMC 2026 earning call series brought no surprises. CC Wei has done more than 30 such calls since taking the CEO position in 2018 and he never fails to disappoint. Once again, CC Wei reported numbers above guidance driven by strong demand and flawless execution. This illustrates the benefit of TSMC’s close collaborations and deeply trusted relationships with partners and customers. The TSMC forecast is the most trusted forecast the semiconductor industry will ever see, absolutely.

I do remember the one-time CC Wei did disappoint on an earnings call and that was during COVID which was a painful supply chain lesson for all. CC Wei turned that COVID supply chain experience into a “Why supply chain trust and resilience is so important” master class that goes to the heart of the TSMC mission statement and that is Trust.

“Our mission is to be the trusted technology and capacity provider of the global logic IC industry for years to come.”

As expected, TSMC N5 and N3 accounted for the majority of 2026 revenue meaning that margins are also well above 60% and look to stay that way in the not-so-distant future. TSMC N3 is also fast approaching the 5-year depreciation mark so TSMC corporate margins will only go up from here.

As we discussed before, TSMC N3 is the final node in the record setting FinFET family of process technologies and it has ZERO competition in the merchant foundry business. I remember tracking design wins when N3 was first launched and realizing that TSMC N3 would be the most dominant process node I would ever see in my 40+ year semiconductor career and that is certainly the case as it stands today.

CC Wei: In Taiwan, we are adding a new 3-nanometer fab to our GIGAFAB cluster in Tainan Science Park. Volume production is scheduled for the
first half of 2027. In Arizona, our second fab will also utilize 3-nanometer technologies. Construction is already complete and volume
production will begin in the second half of 2027. In Japan, we now plan to utilize 3-nanometer technology in our second fab and volume
production is scheduled in 2028.

CC Wei also discussed moving more N5 capacity to N3. Samsung has reportedly fixed their yield problems at 5/4nm so it makes complete sense for TSMC to focus on the higher margin N3 process technologies. Besides, it is easier to move a TSMC N5 design to TSMC N3 than to Samsung 4nm and much easier than moving a design to Samsung 3/2nm (GAA) so CC Wei’s strategy is clear and sound.

CC Wei: Next, let me talk about our N2 capacity expansion plan. Our practice is to prioritize the land in Taiwan to support the fast ramp of our newest
node due to the need for tight integration with R&D operations. Today, our new node, N2, has already entered high-volume manufacturing
in the fourth quarter of 2025 with good yield. N2 is ramping successfully in multiple phases at both Hsinchu and Kaohsiung site, supported
by strong demand from both smartphone and HPC/AI applications.

In regards to TSMC N2, TSMC’s N3 dominance not only sets up customers for a smooth transition to the N2 process family, it brings forward the strongest ecosystem of partners the semiconductor industry has ever seen, which is a very big deal. There is little doubt that TSMC will dominate the 2nm process node. I’m just wondering how big the NOT TSMC market will be at 2nm? It was next to zero at 3nm due to the lack of competition. I hope 2nm will be different with Intel Foundry 18AP and Samsung Foundry SF2 offering viable alternatives to TSMC N2, and maybe even Rapidus 2nm.

The call was closed out with a TSMC A14 Status. Will TSMC A14 again dominate the foundry business? Or better yet; How big will the NOT TSMC market be at 14 Angstrom? It is too soon to tell but my guess would be that the NOT TSMC market will continue to grow due to supply chain concerns.

CC Wei: Finally, let me talk about our A14 status. Featuring our second-generation nanosheet transistor structure, A14 will deliver another full-node
stride from N2, with performance and power benefit to address the insatiable need for high performance and energy efficient computing. Compared with N2, A14 will provide 10% to 15% speed improvement at the same power for 25% to 30% power improvement at the same
speed and close to 20% chip density gain.

Our A14 technology development is on track and progressing well. We are observing a high level of customer interest and engagement from both smartphone and HPC applications. Volume production is scheduled for 2028. Our A14 technology and its derivatives will further extend our technology leadership position and enable TSMC to capture the growth opportunities well into the future.

Of course there were references to Elon Musk and Terafab during the Q&A. CC Wei offered Elon Musk some very sound advice:

CC Wei: Again, let me say that it takes two to three years to build a new fab. No shortcuts. And it takes another one to two years to ramp it up. Again,
that’s a fundamental of foundry industry. And whether we try to win them back (Intel and Tesla), actually, they are still our customers and we are very confident in our technology position. And we work very hard to capture every piece of business possible.

Did you get that Elon? No short cuts in semiconductor manufacturing.

In regards to CapEX, TSMC raised CapEX from $40-41B in 2025 to $52-56B in 2026 which is huge! CC Wei mentioned that TSMC would probably be at the high end of that when asked during the Q&A. In my opinion TSMC will definitely be at the high end of that and maybe even higher. It all depends on how well the NOT TSMC market is developing

Also Read:

TSMC Technology Symposium 2026: Advancing the Future of Semiconductor Innovation

Global 2nm Supply Crunch: TSMC Leads as Intel 18A, Samsung, and Rapidus Race to Compete

TSMC Process Simplification for Advanced Nodes

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TSMC Technology Symposium 2026: Advancing the Future of Semiconductor Innovation

TSMC Technology Symposium 2026: Advancing the Future of Semiconductor Innovation
by Daniel Nenni on 03-16-2026 at 10:00 am
Categories: Events, Semiconductor, TSMC

TSMC Technology Symposium 2026

One of my favorite times of the year is coming (sailing season) and my favorite event of the year is coming as the company I most respect will host the best international semiconductor networking event starting here in Silicon Valley.

The 32nd annual TSMC Technology Symposium represents one of the most influential events in the global semiconductor industry. Organized annually, the symposium brings together semiconductor designers, technology partners, researchers, and industry leaders to discuss the latest advancements in chip manufacturing, packaging technologies, and system integration. The 2026 symposium continues this tradition by highlighting major developments in advanced semiconductor nodes, AI computing, and system-level innovations that will shape the future of electronics.

To me this really is a collaboration victory lap inside the semiconductor ecosystem acknowledging the amazing products we as semiconductor professionals have brought to life. World Changing Technology, and if I may say, World Saving Technology that allows us to live the lives we live today, absolutely.

The event will be held as part of TSMC’s global symposium series, beginning at my favorite location, the Santa Clara, California, and followed by additional sessions in Asia and Europe. These events provide customers and technology partners with updates on TSMC’s semiconductor roadmap and opportunities to collaborate on next-generation chip designs. The symposium focuses on both process technology improvements and the ecosystem required to support modern integrated circuit development.

One of the central themes of the 2026 Technology Symposium will be the rapid growth of artificial intelligence and HPC applications. AI workloads demand extremely powerful processors capable of handling massive data processing and machine learning tasks. TSMC emphasized how advanced semiconductor manufacturing nodes enable higher transistor densities, improved performance, and lower energy consumption, critical requirements for AI data centers, cloud computing infrastructure, and edge devices. The symposium demonstrated how TSMC’s technologies are designed to support these increasingly complex workloads.

Another important focus is the advancement of 2nm-class and angstrom-era semiconductor technologies. TSMC has been preparing for the transition from FinFET to angstrom-scale processes with advanced packaging, representing the next stage of semiconductor scaling. A notable technology in this roadmap is the A16 process, which is expected to enter production in the second half of 2026. This node introduces innovations such as nanosheet transistor structures and backside power delivery, known as Super Power Rail. By delivering power from the backside of the chip rather than the front, this architecture improves signal routing efficiency and supports the high current requirements of advanced processors used in AI and high-performance computing systems.

The symposium will also highlight the importance of system-level innovation, not just transistor scaling. Modern semiconductor performance improvements increasingly rely on advanced packaging technologies, heterogeneous integration, and chiplet-based architectures. Instead of building a single large monolithic chip, designers can combine multiple specialized chiplets in one package to achieve higher performance and flexibility. TSMC’s advanced packaging solutions enable this integration while maintaining high bandwidth communication between chip components.

Another significant aspect of the event is the emphasis on the TSMC ecosystem. Semiconductor manufacturing requires collaboration between many companies, including EDA vendors, IP providers, and system developers. The Technology Symposium allows these partners to demonstrate how their tools and technologies work together with TSMC’s process nodes. In addition, the event often features an Innovation Zone, where startups and emerging companies showcase new semiconductor technologies and design solutions.

The broader semiconductor market context will also influence discussions at the symposium. Demand for advanced chips has increased dramatically due to the growth of AI, data centers, and high-performance computing systems. TSMC has responded by rapidly expanding its manufacturing capacity and investing heavily in new fabrication facilities worldwide. These investments are intended to ensure that the company can meet the rising demand for advanced nodes while maintaining its leadership in semiconductor manufacturing.

Bottom line: The 2026 TSMC Technology Symposium highlights the rapid evolution of semiconductor technology and the critical role that advanced manufacturing plays in enabling future computing systems. From breakthroughs in angstrom-scale process nodes to innovations in packaging and AI computing, the event demonstrated how TSMC continues to push the boundaries of chip design and production. As computing demands continue to grow, the technologies presented at the symposium will play a vital role in shaping the next generation of electronic devices, data centers, and intelligent systems throughout the world.

I hope to see you there!

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Global 2nm Supply Crunch: TSMC Leads as Intel 18A, Samsung, and Rapidus Race to Compete

TSMC Process Simplification for Advanced Nodes

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Global 2nm Supply Crunch: TSMC Leads as Intel 18A, Samsung, and Rapidus Race to Compete

Global 2nm Supply Crunch: TSMC Leads as Intel 18A, Samsung, and Rapidus Race to Compete
by Daniel Nenni on 03-06-2026 at 6:00 am
Categories: Intel Foundry, Samsung Foundry, Semiconductor, TSMC

TSMC 2NM Intel 18A Samsung 2nm Rapidus 2nm

The semiconductor industry is in the midst of a structural supply challenge that’s tightly coupled to exploding demand for advanced chips, especially those used in AI, HPC, and next-generation mobile and consumer devices. At the center of this vortex is the 2nm class of manufacturing technology, representing one of the most complex and expensive transitions in semiconductor history due to its reliance on nanosheet or GAA transistor architectures and extremely precise lithography tools.

TSMC and the 2 nm Capacity Crunch

TSMC’s N2 process node officially entered volume production in late 2025, and early estimates of yield and ramp have been strong enough that the company is aggressively increasing capacity. N2 promises up to 15 % performance gains or substantial power reductions versus previous nodes, making it extremely attractive for next-generation AI accelerators and flagship mobile chips.

The demand has been remarkable! Reports from the trenches indicate that much of TSMC’s N2 capacity is effectively sold out through 2026, with major customers like Apple, Nvidia, Qualcomm, and AMD reportedly locking in large shares of the initial output. This is partly because modern AI accelerators require much more wafer real estate per chip than traditional mobile processors, which exacerbates capacity constraints.

To meet this demand, TSMC has outlined plans to expand production aggressively across multiple fabs, including Hsinchu Baoshan and Kaohsiung in Taiwan and other international sites, with targets that could see monthly wafer starts reach well into six figures by 2026–2028. TSMC’s CAPEX is also a tell for things to come. In 2024 it was $29.8 billion, 2025 a 37% increase to $40.9 billion and a record $52-56 billion in 2026. What this tells me is that TSMC will again dominate 2nm as it did 3nm without question.

Intel’s 18A Process: A Competitive Alternative But Not a Complete Buffer

Intel’s 18A node is part of its post-Intel 7 roadmap and is roughly classed in the same generational tier as 2nm class processes. It introduces both RibbonFET (a version of GAA) and PowerVia backside power delivery, which are intended to boost performance and power efficiency. Intel was first to production quality GAA and first to BSPD, semiconductor innovation at its finest.

Intel started production of 18A in 2025 targeting its own processors such as Panther Lake, but its use as a foundry alternative for external customers remains limited compared. While 18A yields have improved as of mid-2025, they are generally considered behind TSMC’s N2 yields and Intel’s own foundry ecosystem is still small relative to TSMC’s global customer base.

Intel’s strategy is two-pronged: support its internal product leadership and expand foundry services but it has historically struggled to win significant external foundry demand, a key reason why it has not yet materially alleviated the broader industry’s 2nm class capacity squeeze. With Lip-Bu Tan as CEO that has changed of course. The semiconductor Made in America brand has never been stronger, Intel will sign wafer agreements for 18A and 14A from the top semiconductor companies, without a doubt.

Samsung’s 2 nm: Efforts Competitive But Challenged

Samsung was one of the first to deploy GAA technology on a smaller scale starting with its 3nm node, and has planned 2nm production (often referred to as SF2) as an extension of this progress. It has invested heavily in facilities such as the Taylor, Texas fab with the goal of hitting mass production timelines in 2026.

Despite this, Samsung has faced challenges around yield stability and customer adoption. While it offers very competitive pricing, the combination of yield issues and weak customer mindshare means that Samsung is not a viable alterative to TSMC for high-volume 2nm orders. Trust is the foundation of the semiconductor industry and without predictable yield there can be no trust.

Rapidus: A New Entrant Trying to Carve Out Niche 2 nm Capacity

One of the most intriguing developments in recent years has been the emergence of Rapidus, a Japan-based foundry backed by government and major corporate investors. Rapidus aims to begin 2 nm class chip production around 2027, with plans to ramp monthly wafer production significantly within a year of launch.

From what I have learned about Rapidus over the last year, there is little doubt in my mind that they will succeed. In fact, Rapidus just raised another $1.7B for a total of $11.3B in combined government subsidies and private investment. While this is a significant sum, it represents about 40% of the $32 billion the company estimates it will need for full-scale mass production of 2-nanometer chips by 2027 so stay tuned.

Unlike the giants, Rapidus is not attempting to directly compete on sheer volume, but rather offering “short turnaround times” and tailored services, which could appeal to custom chip designers, domestic Japanese technology firms, and organizations needing smaller-lot, highly customized silicon.

Though still years behind TSMC in mass production timing and total capacity, Rapidus represents a strategic move by Japan to regain presence in advanced semiconductor manufacturing and create additional supply chain options in a market heavily concentrated among a few players.

The Broader Context: A Global Capacity Tightrope

The combined reality of TSMC’s dominant position, Intel’s internal and emerging foundry efforts, Samsung’s technically capable but constrained 2nm push, and the Rapidus niche entry creates a semiconductor landscape in which demand continues to outrun supply at the highest performance nodes. Even as worldwide fab capacity grows, the pace of AI adoption and the strategic value companies place on leading-edge silicon means securing wafer slots early has become mission-critical for tech giants and a formidable bottleneck for others.

Bottom line: The 2nm capacity crunch isn’t a short-term supply hiccup, it is a fundamental outcome of how advanced computing, AI, and custom silicon strategies are reshaping the global semiconductor ecosystem for years to come. The strength of the foundry business has always been based on mutil-sourcing and we need to get that supply chain strength back, absolutely.

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TSMC Process Simplification for Advanced Nodes

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TSMC Process Simplification for Advanced Nodes

TSMC Process Simplification for Advanced Nodes
by Daniel Nenni on 02-22-2026 at 4:00 pm
Categories: FinFET, Lithography, Semiconductor, TSMC
3 Comments

TSMC Patent US10692720B2

In the modern world, the semiconductor industry stands at the heart of technological innovation. From smartphones and laptops to advanced medical devices and artificial intelligence systems, nearly every piece of contemporary electronics depends on increasingly sophisticated microchips. Among the leading companies driving this progress is Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC), the world’s largest pure-play semiconductor foundry. Through continuous research, advanced manufacturing techniques, and aggressive scaling strategies, TSMC has played a pivotal role in pushing the boundaries of what is possible in chip fabrication.

Patent US10692720B2

As semiconductor technology advances, one of the most critical goals is scaling down device dimensions. Smaller transistors allow for higher device density, faster switching speeds, and lower power consumption. However, shrinking dimensions introduces immense engineering challenges. At technology nodes such as 5nm and beyond, even minute variations in patterning can significantly impact device performance and yield. Achieving precise control over distances between features, such as the “end-to-end” spacing between adjacent structures, becomes increasingly difficult as these distances approach tens of nanometers.

Traditional lithographic processes often require multiple patterning and etching steps to achieve extremely tight spacing. In earlier approaches, forming patterns with very small end-to-end distances might involve three separate lithography steps combined with multiple etching stages. Each additional step increases production time, cost, and the potential for alignment errors. Overlay inaccuracies between masks can lead to critical dimension variations, negatively affecting device reliability and manufacturing yield. Therefore, reducing the number of processing steps while maintaining or improving precision is a key objective in advanced semiconductor fabrication.

One important innovation involves using a single lithographic process combined with carefully engineered etching techniques to achieve sub-35 nm end-to-end distances. Instead of relying on multiple pattern transfers, this approach begins with forming unidirectional features in a photoresist layer using advanced lithography, such as EUV lithography. EUV uses very short wavelengths of light to define smaller features than previously possible with deep ultraviolet systems. By carefully designing the initial pattern and then applying a controlled angled etch process, the effective length of features can be modified without changing their width.

The angled etch technique is particularly significant. By directing ion beams at specific angles relative to the substrate surface, engineers can selectively trim or extend certain dimensions of patterned structures. For example, the length of a feature along one direction can be increased, thereby reducing the end-to-end spacing between neighboring features. This allows a final pattern to achieve tighter spacing than originally defined in the photolithography mask. Importantly, this method maintains the critical width dimension while adjusting only the desired axis, enabling precise dimensional control.

Such process optimization provides several advantages. First, it reduces the number of required lithography steps from three to one, cutting down cycle time and manufacturing costs. Lithography is one of the most expensive and time-consuming steps in semiconductor fabrication, so eliminating even a single lithography stage can yield substantial economic benefits. Second, fewer process steps reduce the risk of cumulative defects and misalignment errors, improving overall yield and device reliability. Third, streamlined processing enhances throughput in high-volume manufacturing environments, enabling faster delivery of advanced chips to market.

In devices such as FinFETs, which are widely used at advanced nodes, precise pattern control is especially crucial. FinFET architectures rely on three-dimensional channel structures that improve electrostatic control compared to planar transistors. However, their 3D geometry increases fabrication complexity. Maintaining consistent spacing between contacts, gates, and interconnects ensures proper electrical isolation and performance. Techniques that achieve tighter end-to-end distances without increasing process complexity directly support the continued scaling of FinFET and future transistor architectures.

Ultimately, innovation in semiconductor manufacturing is not just about making features smaller; it is about doing so efficiently, reliably, and economically. Companies like TSMC continue to invest heavily in process integration, materials engineering, and advanced patterning technologies to sustain progress beyond the 5nm node. By combining advanced lithography with creative etching strategies, the industry can overcome scaling barriers that once seemed insurmountable.

Bottom Line: As global demand for computing power grows driven by artificial intelligence, 5G communications, autonomous vehicles, and high-performance computing, the importance of such innovations will only increase. The ability to control nanometer-scale distances with extreme precision represents not just a technical achievement, but a foundational capability that shapes the future of modern technology.

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TSMC and Cadence Strengthen Partnership to Enable Next-Generation AI and HPC Silicon

TSMC and Cadence Strengthen Partnership to Enable Next-Generation AI and HPC Silicon
by Daniel Nenni on 02-15-2026 at 6:00 pm
Categories: AI, Cadence, EDA, Semiconductor, TSMC

TSMC WAFER

TSMC continues to reinforce its leadership in advanced semiconductor manufacturing through its deepening collaboration with Cadence Design Systems. The expanded partnership focuses on enabling next-generation artificial intelligence and high-performance computing innovations by aligning advanced electronic design automation, 3D-IC technologies, and silicon-proven intellectual property with TSMC’s most advanced process nodes and packaging platforms.

At the heart of this collaboration is support for TSMC’s cutting-edge process technologies, including N3, N2, and A16™, which are critical for meeting the escalating performance, power efficiency, and scalability demands of AI workloads. Cadence’s AI-driven design flows have been optimized and validated for these nodes, allowing customers to achieve superior power, performance, and area outcomes while accelerating time to market. These flows leverage machine learning–based optimization to address the growing complexity of advanced-node designs, particularly for large-scale AI accelerators and HPC processors.

TSMC’s roadmap toward even more advanced technologies is further strengthened by joint development efforts with Cadence on future nodes, including the upcoming A14 process. Early EDA flow collaboration and PDK readiness ensure that customers can begin design work sooner, reducing risk and enabling faster adoption of next-generation silicon technologies. This early alignment between foundry and EDA provider is increasingly vital as design margins shrink and integration challenges intensify at advanced nodes.

Beyond transistor scaling, the partnership plays a critical role in advancing TSMC’s 3DFabric® platform, which enables heterogeneous integration through advanced packaging and die stacking. Cadence’s comprehensive 3D-IC solutions support a wide range of TSMC 3DFabric configurations, providing automation for bump connections, multi-chiplet physical implementation, and system-level analysis. AI-driven tools such as Clarity™ 3D Solver and Sigrity™ X enable accurate signal integrity, power integrity,  and thermal analysis, helping designers manage the complexities of large, multi-die systems.

Photonics integration is another area of collaboration, particularly through support for TSMC’s Compact Universal Photonic Engine (COUPE™). By combining Cadence’s Virtuoso® Studio and Celsius™ Thermal Solver with TSMC-developed productivity enhancements, customers can more effectively model thermal and electrical interactions in photonic and electronic systems. This capability is increasingly important for AI and data center applications, where power density and thermal management directly impact system reliability and performance.

A key pillar of the Cadence and TSMC partnership is the availability of design-in-ready, silicon-proven IP on advanced nodes such as TSMC N3P. Leading-edge memory and interface IP, including HBM4, LPDDR6/5X, DDR5 MRDIMM Gen2, PCIe® 7.0, and UCIe™, addresses the growing memory bandwidth and interconnect challenges faced by AI systems. These IP offerings enable customers to scale compute performance efficiently while overcoming bottlenecks associated with data movement and power consumption.

Bottom line: Together with the broader Open Innovation Platform® ecosystem, TSMC and Cadence are streamlining the path from design to silicon. By integrating AI-driven EDA, advanced packaging solutions, and next-generation IP with TSMC’s manufacturing leadership, the partnership empowers customers to deliver faster, more energy-efficient AI and HPC solutions. As AI adoption accelerates globally, this close collaboration positions TSMC at the center of the AI semiconductor super-cycle, enabling innovation across the entire value chain, from process technology to system-level integration.

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TSMC vs Intel Foundry vs Samsung Foundry 2026

TSMC vs Intel Foundry vs Samsung Foundry 2026
by Daniel Nenni on 02-13-2026 at 6:00 am
Categories: FinFET, GAA, Intel Foundry, Samsung Foundry, Semiconductor, TSMC
2 Comments

TSMC vs Intel Foundry vs Samsung Foundry

The global semiconductor industry sits at the foundation of modern technology, powering everything from smartphones and cloud data centers to artificial intelligence, automobiles, and national defense systems. At the center of advanced chip manufacturing are three major players: TSMC, Samsung Foundry, and Intel Foundry. Each represents a distinct manufacturing model and strategic philosophy, and together they form a competitive landscape that is essential for innovation, resilience, and long-term industry health.

TSMC is the undisputed leader in pure-play foundry manufacturing. By focusing exclusively on manufacturing and avoiding competition with its customers in chip design, TSMC has built deep trust with fabless companies such as Nvidia, AMD, Apple, and Qualcomm. This focus has allowed TSMC to lead in process technology, consistently delivering the most advanced nodes such as N5, N3, and the upcoming N2 with strong yields and predictable execution. Its dominance has been especially visible in the AI era, where advanced nodes and packaging technologies like CoWoS have become critical bottlenecks.

Samsung Foundry represents a vertically integrated alternative. As part of Samsung Electronics, it both manufactures chips and designs its own products, including memory, logic, and consumer devices. Samsung has pushed aggressively into leading-edge nodes such as 2nm using gate-all-around (GAA) transistors and continues to invest heavily in advanced packaging and U.S. manufacturing. While Samsung has faced significant challenges in yield consistency compared to TSMC they routinely undercut TSMC wafer pricing. It is hard to figure out the math on that point. Even so, Samsung’s presence provides customers with an important second source at advanced nodes.

Intel Foundry is the most strategically significant entrant into the modern foundry race. Historically a vertically integrated company that designed and manufactured its own chips, Intel is opening its leading edge fabs to external customers while rebuilding its process leadership. Intel’s roadmap includes advanced nodes such as Intel 18A, as well as differentiated capabilities in advanced packaging (EMIB, Foveros) with U.S. based manufacturing. While Intel Foundry is still in the initial stages of winning major external customers, its success would meaningfully rebalance the industry by adding large-scale leading-edge capacity inside the United States.

Competition among these three players is not merely a commercial or political issue, it is structurally critical for the semiconductor ecosystem.

First, competition drives technological progress. Advanced chip manufacturing requires enormous capital investment, deep engineering talent, and long development cycles. Without competitive pressure, there would be less incentive to take risks on new transistor architectures, materials, or manufacturing techniques. The rapid evolution from FinFETs to GAAFET transistors is a direct result of competitive urgency.

Second, competition improves supply-chain resilience. Semiconductors are now a matter of national and economic security. Over-reliance on a single foundry or region increases vulnerability to geopolitical tensions, natural disasters, and capacity shocks. A competitive landscape with strong players in different regions reduces single-point-of-failure risk for governments and industries alike.

Third, customers benefit from choice and leverage. Fabless chip designers depend on foundries not just for wafers, but for co-optimization across design, packaging, and manufacturing. When customers have alternatives, they gain negotiating power on pricing, capacity allocation, and long-term roadmap alignment. This keeps foundries responsive to customer needs rather than dictating terms.

Finally, competition fuels ecosystem growth. Foundries anchor vast networks of equipment suppliers, materials companies, EDA vendors, and OSAT partners. When multiple foundries invest aggressively, the entire ecosystem advances faster, benefiting innovation well beyond any single company.

Bottom line: TSMC, Samsung Foundry, and Intel Foundry are not redundant competitors they are essential counterweights. The semiconductor industry needs all three to succeed, because competition ensures innovation, resilience, and sustainable growth in one of the most strategically important industries in the world, absolutely,

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TSMC & GCU Semiconductor Training Program: Preparing Tomorrow’s Workforce

TSMC & GCU Semiconductor Training Program: Preparing Tomorrow’s Workforce
by Daniel Nenni on 02-08-2026 at 2:00 pm
Categories: Semiconductor, TSMC

TSMC GCU Semiconductor Training Program

The expansion of semiconductor manufacturing in the United States, particularly with TSMC’s multi-fab campus in Phoenix, Arizona, has created a significant need for skilled technical workers. To meet this demand, TSMC has partnered with educational institutions, including Grand Canyon University (GCU), to launch innovative training pathways aimed at preparing individuals for careers in semiconductor fabrication and operations. This partnership is part of a broader ecosystem effort involving government, workforce boards, community colleges, and universities working together to develop a sustainable talent pipeline for the semiconductor industry.

Why the Program Exists

Semiconductor manufacturing is one of the most technically demanding and high-technology sectors in the global economy. Operating advanced fabrication facilities, or “fabs”, requires talent with specialized skills in automated systems, precision processes, cleanroom operations, and semiconductor science. When TSMC announced its Arizona investment, one of the key challenges highlighted was the shortage of locally available semiconductor workforce talent with requisite technical skills. In response, the company and regional partners have collaborated on training and apprenticeship programs to build that talent ecosystem locally.

Program Structure and Partnerships

The TSMC-GCU semiconductor training program, formally known as the Manufacturing Specialist Intensive Pathway, is an industry-aligned educational pathway created to prepare participants for technical roles within semiconductor manufacturing. This initiative is part of a broader suite of workforce development efforts that also include registered apprenticeship programs, technician training with community colleges and Northern Arizona University, and other industry partnerships.

At its core, the program with Grand Canyon University focuses on equipping individuals with practical skills that map directly to Manufacturing Specialist roles at TSMC’s Phoenix fabs. The curriculum encompasses semiconductor fundamentals, wafer fabrication processes, standard operational procedures, and factory-floor workflows, all of which are foundational knowledge areas for anyone seeking to enter semiconductor manufacturing.

Program Details

Duration & Format: The program typically runs over a 15-week period, blending classroom instruction with industry-relevant learning experiences designed to mirror real semiconductor manufacturing environments.

Credentialing: Participants earn a certificate of completion from GCU, along with 16 college credit hours, and industry-recognized professional credentials from the Institute of Electrical and Electronics Engineers (IEEE), which helps validate competencies to employers.

Target Audience: The training is geared toward a wide range of learners — from high school graduates and career changers to individuals already in the workforce seeking new tech-focused opportunities.

Pathway to Employment: Successful participants gain not only educational credentials but also a competitive advantage when applying for semiconductor technician, manufacturing specialist, or related technical roles at TSMC or other semiconductor firms in Arizona.

Broader Workforce Strategy

While the GCU partnership is a key piece of the talent development puzzle, it sits within a larger regional workforce strategy. TSMC’s Registered Technician Apprenticeship program, supported by the State of Arizona, the City of Phoenix, and institutions like Estrella Mountain Community College, Northern Arizona University, and other partners, offers multi-year apprenticeship pathways in equipment, process, and facilities technician roles that combine classroom instruction with paid on-the-job training.

These programs are designed to address both entry-level and advanced technical needs. Apprentices typically work hands-on in real semiconductor environments while earning credit and experience, which can lead to stackable credentials and even associate or bachelor’s degrees when combined with college coursework.

Impact and Future Prospects

The TSMC-GCU semiconductor training program underscores the importance of public-private educational collaboration in scaling a skilled workforce fast enough to match the pace of industrial growth. By equipping participants with relevant technical knowledge and credentials recognized by both academia and industry, the program not only fills immediate labor gaps but also fosters long-term career opportunities in a high-tech sector that is becoming increasingly critical for U.S. competitiveness.

Bottom line: This initiative helps bridge the transition from education to employment in a field where the demand for skilled workers is projected to grow as semiconductor manufacturing continues to expand across the United States.

GCU and TSMC’s MSI Pathway Webinar

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