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TSMC’s 5nm 0.021um2 SRAM Cell Using EUV and High Mobility Channel with Write Assist at ISSCC2020

TSMC’s 5nm 0.021um2 SRAM Cell Using EUV and High Mobility Channel with Write Assist at ISSCC2020
by Don Draper on 03-06-2020 at 6:00 am
Categories: Events, Foundries, TSMC
1 Comment

Fig. 1 Semiconductor Technology Application Evolution

Technological leadership has long been key to TSMC’s success and they are following up their leadership development of 5nm with the world’s smallest SRAM cell at 0.021um 2 with circuit design details of their write assist techniques necessary to achieve the full potential of this revolutionary technology. In addition to their groundbreaking device developments such as High Mobility Channel (HMC) they are the leading implementers of Extreme Ultra-Violet (EUV) patterning to enable higher yield and shorter cycle time at this advanced node.

Semiconductor technology evolution has been driven by the application landscape which in the current phase of High-Performance Computing (HPC), Artificial Intelligence (AI) and 5G communication requires the highest performance with limited power dissipation as illustrated in Fig. 1.

Fig. 1 Semiconductor Technology Application Evolution

This technology was described by TSMC at IEDM 2019, where they described their 5 nm process which uses more than 10 Extreme Ultra-Violet (EUV) mask patterning steps replacing three or more immersion mask steps each and High Mobility Channel (HMC) technology for higher performance. This technology has been in risk production since April of 2019 and will be in full production 1H2020.

The implementation of this technology for the development of high- performance SRAM bit cells and arrays was described by Jonathan Chang, et al at ISSCC2020.

The quantizing of FinFET transistor sizing continues to be a major challenge and forces all transistors in the high-density 6T SRAM cell to use only a single fin. The design is optimized through Design-Technology Co- Optimization (DTCO) to give high performance and density as well as high yield and reliability. SRAM bit cell scaling for 2011 to 2019 is shown in Fig. 2.

Fig. 2. SRAM bit cell scaling is shown for 2011 to 2019.

It can be noted that the cell size reduction rate from 2017 to 2018 to 2019 is much slower than the rate for preceding years 2011 to 2017, showing that SRAM cells have not been scaling at the same rate as logic in general. At IEDM 2019, the 5nm process was quoted to have 1.84x logic density improvement compared to 1.35x SRAM density improvement. Further area reduction utilizing Flying Bit Line (FBL) architecture is implemented for 5% area savings. The layout of the 5nm cell is shown in Fig. 3.

Fig. 3. Layout of the high-density 6T SRAM bit cell.

For power reduction, a key approach is lowering the minimum operating voltage Vmin of the SRAM array. The increased random threshold voltage variation in this latest technology limits Vmin which in turn limits the opportunities for power reduction. The SRAM voltage scaling trend is shown in Fig. 4, where the blue line indicates the Vmin without write assist and the red line indicates Vmin with write assist, showing great benefit of write assist with each generation. It will be observed that the Vmin from 7nm to 5nm shows very little improvement, indicating that further power reduction must be gotten from improvements in write assist generation circuits. This article will describe the major write assist methods to enable lower Vmin in operation, negative bit line (NBL) and Lower Cell VDD (LCV).

Fig. 4. SRAM cell voltage scaling trend without write assist (blue line) and
with write assist (red line).

The SRAM cell schematic is shown in Fig. 5 showing contention during write between the PU and pass-gate transistor PG. A stronger PU transistor would yield a higher read stability, but it degrades the write margin significantly and results in a contention write Vmin issue.

Fig. 5. SRAM cell schematic showing contention during write between the
PU and pass-gate transistor PG.

The first method to improve the write Vmin is to lower the bit line voltage during write, called Negative Bit Line or (NBL). This method has been employed for several years, using a MOS capacitor to generate a negative bias signal on the bit line, but this write assist circuitry results in area overhead. Furthermore, a fixed amount of MOS capacitance induces over boosted NBL level for short BL configuration and may led to dynamic power overhead in short bit lines, as shown in Fig. 6.

Fig. 6. Fixed amount of MOS capacitance induces over-boosted NBL level
for short BL configuration and may lead to dynamic power overhead
avoided by the metal cap NBL.

The overboost and the MOS capacitor area issues can be avoided by using a metal capacitor-coupled scheme based on coupled metal tracks laid out on top of the upper metal of the SRAM array. To avoid the overboost, the metal capacitor length can be modulated with the SRAM array bit line length, saving dynamic power. Furthermore, the coupled NBL level can also be adjusted to compensate the loss of write ability induced by BL IR drop on the far-side bit cell.

The NBL enable signal (NBLEN) in Fig. 7 drives one side of the metal capacitor C1 negative which couples a negative bias signal at the virtual

ground node NVSS which then passes through the write driver WD and column multiplex to the selected bit line.

Fig. 7. The NBL enable signal (NBLEN) couples the configurable metal
capacitor C1 to NVSS.

The NBL coupling level with different bit line configurations, Fig. 8, showing that the configurable metal capacitor C1 can track with bit line length so that the variation of the coupling NBL level with different Bit line length can be mitigated.

Fig. 8. NBL coupling level with different bit line configurations showing the
longer 256bit bitline (blue) having an extended NBL boosted level.

The second method of write assist is to Lower the Cell VDD, (LCV). The conventional techniques of LCV require a strong bias or an active-divider to adjust the column-wise bit cell power supply during write operation, but these techniques consume a huge amount of active power across operating time. Pulse Pull-down (PP) and Charge Sharing (CS) techniques are two alternative solutions but precise timing is difficult for PP, so CS is proposed using metal wire charge sharing capacitors on top of the array as shown in Fig. 9.

Fig. 9. Charge Sharing (CS) for Low Cell VDD (LCV) for write assist using
CS metal tracks on top of the SRAM array.

In write operation, the LCV enable signal (LCVEN) goes high, it turns off the pull low NMOS (N1) to isolate the charge sharing capacitor C1 from ground. A column is selected by COL[n:0] to turn the header P0 off and isolates the array virtual power rail CVDD[0] from true power VDDAI. Because the metal wire capacitance scales along with the size of the bit-cell array, it also benefits the SRAM compiler design and provides a relatively constant charge sharing voltage level with varied BL configurations. The charge sharing level is determined by metal capacitance ratio of CVDD and the charge sharing metal track. Fig. 10 shows three LCV-VDD ratios are implemented for 6%, 12% and 24%.

Fig. 10. Three LCV-VDD ratios are implemented for 6%, 12% and 24%.
With write assist turned off, Vmin is constrained by write failure. Measured
results with Write Assist in Fig. 11 show NBL improves Vmin by 300mV and 24% LCV improves Vmin independently by over 300mV.

Fig. 11. Measured results of (a) metal capacitor-boosted Write Assist
WAS-NBL scheme and (b) metal charge-sharing capacitor WAS-LCV
scheme.

Performance of the 5nm process is enhanced by the High Mobility Channel with ~18% drive current gain shown in Fig. 12. This technology was described in detail at IEDM2019.

Fig. 12. High Mobility Channel (HMC) performance gain of ~18%.
This performance gain is exemplified by the high-speed SRAM array for
L1 cache application achieving 4.1Ghz cycle time t 0.85V shown in the
shmoo plot in Fig. 13.

Fig. 13. Shmoo plot of the HD SRAM array for use as a high performance
L1 cache showing 4.1 GHz at 0.85V. The measured results are based on the 135 Mb test chip shown in Fig. 14.

Fig. 14. 135 Mb test chip in 5 nm HK-MK FinFET with High Mobility
Channel (HMC) and 0.021um 2 SRAM bit cell.

In summary, the detailed circuit design techniques described here enable the product developer to get the maximum advantage from this leading technology. An important device development approach is to do Design- Technology Co-optimization (DTCO) between product/circuit designers and process developers responsible for product yield and reliability.

ALSO READ: TSMC Unveils Details of 5nm CMOS Production Technology Platform Featuring EUV and High Mobility Channel FinFETs at IEDM2019

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TSMC Unveils Details of 5nm CMOS Production Technology Platform Featuring EUV and High Mobility Channel FinFETs at IEDM2019

TSMC Unveils Details of 5nm CMOS Production Technology Platform Featuring EUV and High Mobility Channel FinFETs at IEDM2019
by Don Draper on 02-05-2020 at 10:00 am
Categories: Events, Foundries, TSMC
18 Comments

Diagram of BEOL metallization comparing EUV vs. immersion photolithography

Back in April, 2019, TSMC announced that they were introducing their 5 nm technology in risk production and now at IEDM 2019 they brought forth a detailed description of the process which has passed 1000 hour HTOL and will be in high volume production in 1H 2020.  This 5nm technology is a full node scaling from 7nm using smart scaling of major design rules (gate, fin and Mx/Vx pitches) for improved yield featuring an SRAM cell of 0.021um2 and a declining defect density D0 that is ahead of plan.

A primary reason for the success of the 5nm technology platform is the implementation of Extreme Ultra-Violet (EUV) photolithography.  Fully-fledged EUV replaces at least four times more immersion layers at cut, contact, via and metal line masking steps for faster cycle time, better reliability and yield. Total mask count in 5nm is several masks less than in the previous 7nm node.  Fig. 1 shows how one EUV mask replaced five immersion masks yet produces better patterning fidelity, shorter cycle time and fewer defects.

Fig. 1. Diagram of BEOL metallization comparing EUV vs. immersion photolithography showing how one EUV mask replaced five immersion patterning layers with better patterning fidelity, shorter cycle time and fewer defects.

FinFETs have been used in four generations from the 16nm node to 7nm, but performance as a function of channel mobility has been stagnant.  To address this, the High Mobility Channel (HMC) was implemented to increase performance.  The TEM in Fig. 2 shows the fully-strained HMC lattice constant interfaced with the Si lattice constant. The diffraction pattern confirmed HMC strain.

Fig. 2. Diagram showing finFET cross-section TEM showing fully-strained HMC lattice constant interfaced with the Si lattice constant.  The second plot shows higher leakage vs drive current of the silicon vs HMC transistors. The third plot shows the channel stress in GPa vs channel depth from the fin top to the fin bottom. The diffraction pattern shown confirms the HMC strain.

The HMC finFET has excellent Id-Vg characteristics as shown in Fig. 3 and produces ~18% more drive current than the Si finFET.  Figure-of-Merit (FOM) ring oscillator standby power also correlates well to transistor leakages.

Fig. 3. Chart showing drain current vs gate voltage (Id vs Vg) characteristics of the High Mobility Channel (HMC) transistors for different drain voltages.  The second plot shows the off-current ranges, Ioff-N and Ioff-P and the relative impact on standby current of the seven different Vt’s available in the technology. The currents in both diagrams are in logarithmic scale with one decade per division.  The Drain-Induced Barrier Lowering (DIBL) is 45mV and 35 mV and the swing is 69mV and 68mV for p-channel and n-channel transistors respectively.

This 5nm CMOS platform technology is a full node scaling from the 7nm process described in IEDM 2016. The availability of up to seven Vt’s for each transistor type, shown in Fig. 4, enables product design to meet the needs of power efficiency in mobile SoC as well as peak speed requirements of HPC.

Fig. 4. Chart of up to seven Vt’s available in N5 showing standby power in uW vs speed in GHz for N5 and N5 HPC compared to N7 to meet maximum power efficiency for mobile and peak speed in HPC.   eLVT offers 25% faster peak speed over 7nm.  Silicon data close to matching FOM ring speed vs stand-by power.

New HPC features are the extremely Low VT (eLVT) transistor with 25% faster peak speed over 7nm   and three-fin standard cells for an additional 10% performance increase. The technology is available for 3D chip stacking using hybrid bonding.   In addition to impressive density and performance gains relative to 7nm, the technology has achieved 1000 hour HTOL qualification with improved stress aging characteristics relative to the 7nm technology. The high-yielding SRAM and logic defect density D0 is ahead of plan. Technological achievements enabling this progress feature full-fledged implementation of EUV and high-mobility channel (HMC) finFETs.

This 5nm platform technology was designed and developed to meet objectives of PPACT(Power, Performance, Area, Cost and Time to Market). Design-Technology Co-Optimization (DTCO) is emphasized for smart scaling, avoiding brute-force scaling which would lead to drastically-increased process cost and yield impact.  Design features such as gate-contact-over-diffusion and unique diffusion termination along with EUV-based gate patterning enable SRAM size reduction and increased logic density.  The 5nm technology offers 15% faster speed at the same power or 30% power reduction at the same speed with 1.84x logic density of the 7nm node , as shown in Fig. 5.

Fig. 5. Plot comparing the speed in GHz vs. the core area in um2 of the N5 technology vs the previous N7. The 5nm technology offers 15% faster speed at the same power or 30% power reduction at the same speed with 1.84x logic density of the 7nm node.

Interconnect delay has a critical impact on product performance and with each generation the interconnect propagation delay has been  getting significantly worse.  Backend metal RC and via resistance is shown in Fig. 6 for generations from N28 to N5. The tightest pitch Mx RC and the Vx Rc are kept similar to the 7nm node by EUV patterning, innovative scaled barrier/liner ESL/ELK dielectrics and Cu reflow.

Fig. 6.  Charts of  normalized BEOL metallization RC product and via resistance vs nodes from N28 to N5 are shown. For the tightest metal pitch, MX RC and via resistance Vx Rc are kept similar to that of the previous 7nm node by EUV patterning, innovative scaled barrier/liner ESL/ELK dielectrics and Cu reflow.

SRAM density and performance/leakage are critical for mobile SoC and for HPC AI. Scaling of SRAM cells with more advanced nodes is becoming more difficult in feature size terms of F 2.  The offered High Current (HC) and the High Density (HD) SRAM cells with cell areas of 0.025um2 and 0.021 um2 respectively are the densest in the industry as shown in Fig. 7. Consistent high yield of the 256 Mb SRAM and logic test chips of >90% peak yield and ~80% average yield (without repair) has been achieved.

Fig. 7.  Chart of published SRAM cell size in um2 vs year of publication. The 5nm HD SRAM cell at 0.021 um2 is the densest offered in the industry.

The Ultra-low leakage ULHD can be used to reduce retention leakage for better power efficiency while higher-speed HSHD SRAM may be used as an alternative to HC SRAM cells to allow ~22% reduction in memory area as shown in Fig. 8.

Fig. 8.  Chart of standby leakage in pA at 0.4V  vs cell current in uA for ULHD, HSHD and standard HD SRAM cells. The Vout vs Vin butterfly curve plots of the 5nm HD SRAM cell  are shown at voltages  from 0.75V down to 0.3V.

The shmoo plot of the 256Mb 0.021 um2 HD SRAM cell with full read/write function is shown down to 0.4V in Fig. 9.

Fig. 9.  Shmoo plot showing Vout vs Vin from 1.0V down to 0.4V of the 256Mb SRAM based on the 5nm 0.021 um2 HD SRAM cell.

The frequency response shmoo plots of the GPU and CPU blocks in the high-yielding logic test chip are shown in Fig. 10.

Fig. 10. Shmoo plots of frequency in GHz vs. voltage for the GPU and CPU blocks respectively in the high yielding logic test chip in the 5nm qualification vehicle.

The 256Mb HD/HC SRAM and logic test chip passed 1000 hour HTOL qualification. The SRAM Vmin showed a negligible shift at 168 hours and passed the 1000 hour HTOL with ~51mV margin as shown in Fig. 11.

Fit. 11.  Plots of log-normal distribution vs Vmin in mV at 168 hours HTOL showing negligible Vmin shift and at 1000 hours HTOL, passing 1000 hours with 51mV margin.

Stress aging data at 0.96 V and 125C on the 5nm FOM ring oscillator made with the High Mobility Channel finFETs shown in Fig. 12 with improved aging relative to the 7nm node.

Fig. 12. Plot showing T50% lifetime(years) vs. stress voltage Vstr of aging study at 125C of N5 HMC finFET ring oscillators and N7 silicon finFET ring oscillators showing improved aging at the 5nm node relative to that at 7nm.

Another important feature for HPC is the metal-insulator-metal (MiM) capacitor formed in the upper layers of the BEOL metallization.  The 5nm node MiM has 4x higher capacitance density than the typical HD-MiM and produces ~4.2% faster Fmax by minimizing transient drooping voltage and achieved ~20mV Vmin reduction in a CPU test chip.

HPC critically depends on high-speed IOs especially SERDES.  By successfully optimizing finFET driving strength and capacitance/resistance with special high-speed devices, PAM-4 SERDES transmitter speed of 112 Gb/s at 0.78 pJ/bit and 130 Gb/s at 0.96pJ/b power dissipation as shown in Fig. 13.

Fig. 13. Plots showing signal characteristics of voltage out in mV vs time in ps of 112 Gb/s and 130Gb/s data transmission in SERDES PAM-4 with 0.78pJ/b and 0.96pJ/b respectively.

In conclusion, TSMC has presented a very competitive technology platform, establishing itself as the leader in best-in-class highest density logic technologies.  Volume production in 1H 2020 will enable leading edge products in advanced SoC for mobile, especially 5G, as well as HPC applications for AI, datacenter and blockchain products which increasingly need high performance with best power efficiency.

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ASML “A Swing to Memory Looms” Nice performance while awaiting Memory bounce

ASML “A Swing to Memory Looms” Nice performance while awaiting Memory bounce
by Robert Maire on 01-24-2020 at 6:00 am
Categories: Lithography, Semiconductor Advisors, Semiconductor Services, TSMC
1 Comment

ASML 2020 Logic Memory
  • Good Q4 & 2019 despite weak memory
  • 2020 will be up year but memory an unknown
  • EUV ramp is on track – no China or memory impact
ASML reports an “in line” Q4 despite industry weak 2019

ASML reported sales of 4B Euros and a nice gross margin of 48% resulting in 2.70 Euros per share in earnings.  Orders came in at 2.4B Euros with roughly 80% coming from logic. Despite 2019 being a down year for semiconductor equipment as a whole, ASML managed to have 8% growth during 2019 as spending in the industry shifted back towards lithography purchases,  We expect this trend of enhanced litho spending to hold true in 2020 as the industry continues its EUV adoption.

Logic (TSMC) remains the biggest driver at roughly 80%
It is interesting to note that ASML was able to keep up its growth despite the fact that memory spend went from the majority of sales in 2019 down to roughly 20% of sales at the close of the year. Despite this huge shift in end market demand the company has maintained good growth.

It obviously helps a lot to have strong backlog and a strong order book to be able to more efficiently manage the ebbs and flows of customer mix as 2019 was not an ebb and flow but more of a stampede away from memory to logic/foundry. It also helps that EUV is obviously focused on foundry/logic so the stampede was to ASML’s benefit as well.

“Focus” changes from making EUV work to making more EUV…..
It is also very clear that now that we are well over the acceptance and HVM hurdle of EUV, attention is now turning to turning out more systems faster. Getting down cycle times and getting the supply chain cranked up while still hard is not as hard as working out the kinks has been over the last few years.

2020 looks to be about 35 EUV tools with an eye towards 50 in 2021.  These seem like reasonable, “doable” targets.  We don’t think we need a full blown memory recovery to get to this years goal of 35 and memory will likely recover soon enough to support a 2021 goal of 50.

There is still a lot of work to be done on high NA but less critical than the original work as high NA is an improvement rather than wholesale change.

Multibeam delay helps KLA
One of the few negative points raised, although minor, was the delay of multibeam.  While not totally unexpected given the complexity, it does give KLA a bit of time to work on their products and counter measures.

In our view now that the war has been won on EUV, ASML can and should shift some more focus and spend to metrology & yield related issues and tools and products as it will also support the infrastructure for EUV going forward.

Memory still an unknown
It was clear from the call and clear in our view that the recovery of the memory industry is very much unclear. While NAND will no doubt recover first and DRAM some time later, the company gave no indication other than “just hoping” that memory recovers.  There was no evidence given nor implied of improved order activity or any other indication of memory spend coming back any time soon.

Like the rest of the industry, the key to a strong up cycle is memory along with foundry/logic both working at the same time….we remain with foundry/logic at roughly 80% of business with memory barely plodding along. This is obviously more of a negative for players like Lam who are much more memory centric.  Even though business at Lam and Applied has picked up of late, its not like the rip roaring memory love fest.

China is a non-issue
There remains a lot of discussion in the press about poor ASML being the ping pong ball in a game between China and the US.  So far we see zero impact from any sales restriction to China.  We expect no near term ill effects on ASML and the real issues and impact are more political than financial.  Though ASML may not be happy to be a pawn it hasn’t impacted their profitability or overall sales. We think there is a higher level of risk of the embargo spreading to US equipment companies that would see more financial impact.

The stocks
Given that the quarter was just in line with no surprises, we expect little movement in an already fully priced stock. There was also nothing surprising nor significantly impactful on other stocks that would drive the group one way or another.  The lack of any sign of memory recovery is a little bit disappointing for the group that has seen its shares on a tear despite the weakness.

All in all no impact and we are not motivated to run out and chase stocks that have already run up nor are we tempted to short stocks that have such unusual support.

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TSMC Q4 2019 “2020 Bellwether” Conference Call Summary

TSMC Q4 2019 “2020 Bellwether” Conference Call Summary
by Daniel Nenni on 01-20-2020 at 6:00 am
Categories: Foundries, TSMC
17 Comments

TSMC Manufacturing Excellence

After returning from a week in Southern China I found the TSMC Q4 2019 conference call even more interesting. In China they are preparing for the New Year’s Celebration so everything is very festive but what struck me hardest was the massive investment in infrastructure and security. Semiconductors are of course a big part of that thus the urgent need for China to be semiconductor-self-sufficient, absolutely.

TSMC of course is a valued partner of China and will benefit the most from China’s continued semiconductor boom. If you read between the lines of the TSMC Q4 conference call you will see it more clearly. First let’s look at the technology parts of the prepared statement:

“16-nanometer and below, accounted for 56% of wafer revenue, up from 51% in the third quarter. On a full year basis, 7-nanometer contribution increased from 9% in 2018 to 27% of wafer revenue in 2019. 10-nanometer was 3% and 16-nanometer was 20%. Advanced technologies accounted for 50% of total wafer revenue, up from 41% in 2018.”

It is interesting to note that TSMC 20nm and 16nm shared fabs where 20nm was the sacrificial lamb and 16nm is the cash cow. It was the same with 10nm and 7nm (cash cow). So, what is going to happen now that TSMC is moving 7nm customers to 6nm and 5nm is ramping up this year? Will TSMC break the cycle and have two cash cows in a row? From what I have been told 6nm is an EXCELLENT process and will be VERY competitive on price / performance with both TSMC and Samsung 5nm. In fact, my guess is that TSMC 6nm will even outperform Intel 10nm on density, yield, and most certainly cost.

“Now let’s take a look at revenue contribution by platform…. On a full year basis, smartphone and IoT led the growth with 12% and 33%, respectively, while HPC, automotive and DCE decreased 8%, 7% and 8%, respectively… Overall, smartphone accounted for 49% of our 2019 revenue; HPC, 30%; and IoT, 8%.”

Remember, in 2019 China is second in TSMC revenue (20%) behind the US (60%) but well in front of the other parts of the world and China revenue is on the rise. My guess is that China will be 25% of TSMC’s revenue in 2020 further out pacing Japan, Korea, Taiwan, and the EU, who are all in single digits.

The TSMC smartphone and IoT surge are a very good reflection of the China market.

Samsung is being pushed out of china leaving Apple as the only foreign smartphone supplier in the top 5. Huawei is dominating and Huawei and TSMC go together like peanut butter and jelly. In order to compete the other China smartphone suppliers are forced to follow Huawei into the TSMC ecosystem so it is all about TSMC.

IoT is the interesting one. The number one IoT driver in China is security (cameras) which are EVERYWHERE and backed by AI. 5G is a national priority in China and will increase the abilities of AI on the edge.

For example, in the US we have license plate readers so our local police can identify and recover stolen cars and the criminals that are driving them. The next level is facial recognition where law enforcement can identify known criminals and recover them. China is already at that next level, semiconductors and AI are everywhere and there is no stopping it no matter how you feel about privacy.

“We raised our 2019 CapEx guidance by $4 billion to $14 billion to $15 billion, and we ended up spending $14.9 billion. Our 2020 capital budget is expected to be between $15 billion and $16 billion. Out of the $15 billion to $16 billion CapEx for 2020, about 80% of the capital budget will be allocated for advanced process technologies including 3, 5 and 7-nanometers, about 10% will be spent for advanced packaging and mask-making and about 10% for specialty technologies.”

As I mentioned before, TSMC won the 7nm, 6nm, and 5nm popular vote so do not be surprised if CapEx is again raised and we have another hockey stick of growth in Q4.

“For the full year of 2020, we forecast the overall semiconductor market growth excluding memory to be 8%, while foundry industry growth is forecast to be about 17%. For TSMC, we are confident we can outperform the foundry revenue growth by several percentage points in U.S. dollar term.”

Now that ‘s what I’m talking about… 20% growth. It really is satisfying when hard work pays off.

“Now allow me to talk about our N5 volume production. Our N5 technology is a full node stride from our N7, with 80% logic density gain and about a 20% speed gain compared with 7-nanometer. N5 will adopt EUV extensively and is well on track for volume production in first half this year and with good yield.”

“Finally, I’ll talk about our N3 status. We are working with customers on N3’s design, and the technology development progress is going well. We have many technology options in development and we carefully evaluate all the different approaches. Our decision is based on technology, maturity, performance and cost… We will announce more details about our N3 technology at our TSMC North America Technology Symposium on April 29.“

TSMC N3 will again be FinFET based. We can talk more about this after the Symposium. The Q&A was pretty lame this time but here is the best answer:

“But I can just tell you that whatever you read on the newspaper is not true…”

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The Tech Week that was January 13-17 2020

The Tech Week that was January 13-17 2020
by Mark Dyson on 01-19-2020 at 10:00 am
Categories: China, TSMC

Semiconductor Weekly Summary 1

In a week where the “phase 1” trade deal between US and China was finally signed, here is all the key news from the semiconductor and technology sector around the world.

After 2 years of an ever increasing trade war, the US and China have signed the so called Phase 1 deal aimed at reducing trade frictions.

Just as important as what is in the phase 1 deal are the items that are left out and are the major items to negotiated for the next phase. This BBC article reviews the major items missing which include the issue of China subsidies to companies in of support it’s “Made in China 2025” policy. Also excluded is the ban on Huawei and further reductions in tariffs that still remain. Let’s hope that progress is made on these more difficult items soon.

According to Gartner, last year Intel regained the number 1 slot for semiconductor companies based on global revenue in 2019 as Samsung dropped to number 2 due to the decline in memory prices and sales in 2019. Overall Global semiconductor revenue dropped 11.9% in 2019 compared to a year ago according to Gartner.

2020 is starting off with a brighter forecast for the year. Semiconductor analyst company Future Horizons is predicting that the global semiconductor market will increase to US$451billion in 2020, this is a 10.2% increase compared to 2019.

This optimism is backed up by initial trade data from Korea, where Korean semiconductor exports rose 12% in the first 10 days of 2020 in a sign that the industry is recovering from the negative effects of the trade war. This is the first time the figures have shown growth since October 2018.

TSMC expects to post revenues of between US$10.2 billion and US$10.3 billion in the first quarter of 2020, representing a 1.4% sequential decrease, but up a massive 44% on a year ago. TSMC also set its capex target this year at between US$15 ~16 billion, up from the US$14.9 billion allocated in 2019 with the majority of capex to be spent on advanced process nodes including 7nm, 5nm and 3nm.  TSMC’s Q4 revenue increased to US$10.4bn, up 10.6% sequentially of which 7nm chip shipments accounted for 35% of its total wafer revenues, up from 27% in the prior quarter. Advanced technologies, defined as 16nm and below, accounted for 56% of TSMC’s total wafer sales. In Q4 2019 smartphone revenues accounted for 53% of TSMC’s total wafer revenues, followed by the HPC segment with 29%, IoT with 8%, automotive 4% and digital consumer electronics 3%. In terms of markets, North America remained TSMC’s largest market with a 59% revenue share in Q4 whilst China accounted for 22%. This is up 9% compared to the same period in 2018. With business booming, according to Digitimes, TSMC 7nm process lead time remains at about six months, with tight supply expected to last through 2020

Also according to Digitimes, ASE is rumoured to be supplying to Apple antennas needed for mmWave 5G iPhones and iPad.

Elsewhere AMS has said it is confident it will get shareholder backing for it’s rights issue at it’s EGM on 24th January. The rights issue to raise US$1.84billion will help to partially refinance the US$4.42billion loan AMS took to acquire it’s 59.9% share of Osram.

With the expected recovery of the automotive market and it’s strong demand for SiC products, STMicroelectronics has signed a US$120million multi year supply deal for 150mm Silicon Carbide (SiC) wafers from SiCrystal AG which is part of the ROHM group. The deal adds extra SiC wafer capacity on top of existing deals STM has signed last year with other suppliers like Cree where it signed a multiyear US$250million supply deal and Norstel AB where it has acquired a majority stake in the company.

As a follow to a story last week, where the US put pressure on the Netherlands and ASML to not ship the latest EUV tool to China, the Chinese ambassador is quoted as saying that trade relations between China and the Netherlands would be damaged if ASML is prevented from selling the latest tools to China.

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Samsung spend is up but can it offest TSMC slowing?

Samsung spend is up but can it offest TSMC slowing?
by Robert Maire on 01-17-2020 at 6:00 am
Categories: Semiconductor Advisors, Semiconductor Services, TSMC
1 Comment

TSMC Wafer

Samsung is warming up and spending again
Samsung gave its preliminary report for Q4 and it was well better than prior muted expectations. It doesn’t take long for Samsung’s business units to respond to business trends in either direction and we have already heard of increased spending plans on the part of Samsung.

Samsung has not been shy about spending and has even spent to excess as 2018 bore out.  Samsung is equally not shy about cutting spending when the industry slows. We have heard that Samsung has already started to spend even though the recovery in memory is still in early stages and DRAM is well behind NAND in terms of a recovery.

Obviously this is the Wayne Gretzky philosophy of “skate to where the puck is going, not where it has been”. Samsung is trying to get out in front of an expected memory uptick.

This is despite the fact that we have a ton of excess capacity in idled tools sitting around waiting to be turned back on which could easily satisfy increasing demand.

We think that part of Samsung’s spend is more focused on technology rather than pure capacity spend. Samsung has always tried to best its competitors by staying ahead of the cost/technology curve and one way to lead the way out of the memory slow down would be to have an ability to make money at pricing levels that competitors lose money at.

We certainly don’t expect the “drunken sailor” level of spend that Samsung exhibited in 2018 but rather more focused and cautious spend with a technology leaning.

Will Samsung’s spend offset an eventual TSMC decline? As we have previously mentioned, many times, TSMC is a “seasonal” spender focused on getting to the next node in time for Apple’s fall launch of new Iphones. This means that new tools an technology gets ordered and shipped in Q4 and Q1 to iron out the process in Q2 and ramp production in Q3 for the fall launch. We are currently in the midst of a big seasonal spend cycle for TSMC getting its 5NM act together. It is TSMC’s Q4 spend hockey stick that has gotten the equipment industry off the bottom of the cycle.

But all good things come to an end in this most cyclical of industries and TSMC’s spend will likely slow a bit after Q1 as it focuses its efforts on ramping up all that shiny new equipment for 5NM. The real question is will Samsung’s spending ramp offset the expected slowing of TSMC?  Probably yes…

We also expect a bit of share shift as memory based spend is obviously very different from logic/foundry spend.

BIS – Little known government agency may prove impactfull

Most people don’t know who or what BIS is.  It is a government agency whose acronym BIS stands for “Bureau of Industry & Security”.
With the recent revelation about behind the scenes US pressure on ASML it is clear the government is using an old tool to combat China in the semiconductor industry and that is “national security”.
Its clear that the trade deal has little to no IP protection in it so other means will have to be used to limit the technology flow.
We have suggested that we will likely see more involvement from the government in the form of export licenses/export controls and other methods that are not tariff based.
The mission statement of BIS- “Advance U.S. national security, foreign policy, and economic objectives by ensuring an effective export control and treaty compliance system and promoting continued U.S. strategic technology leadership.”- seems tailor made to be an alternative method to achieve goals that the trade deal didn’t.
We expect to hear more from companies over the next few quarters as the government gets more involved in the regulatory side of trade with China, especially, obviously, in tech.
With think ASML is both the tip of the iceberg and beginning of new phase of government involvement.
While we don’t expect an embargo, we could easily see more scrutiny, more export license issues, denial of export licenses or delays that may impact tech exports to China without an “overt” action.

What will companies report about Q4?

We think companies will generally be more positive. Reports of end product sales have been good. CES 2020 has been very positive and trade concerns have fallen by the wayside.
Memory is getting better. Tech stocks are doing great. Everything is happy.  This is all despite the fact that we are going into a seasonally weak Q1.
In general, companies are not likely to “fight the tape” and will likely talk about the improving environment going forward, probably more so because perceived potential risks are reduced.
2019 wasn’t as bad as it otherwise could have been
At one point, chip equipment companies were looking at a 20% down year versus 2017/18 given memory’s cliff dive. TSMC coming through at the end of the year looks to have limited the downside to a lot less, perhaps on down 10% or so.
The downturn lasted about 4 to 5 quarters spanning the second half of 2018 and first 3 quarters or so of 2019. The downturn spanning over two fiscal years rather than focused in one year has mitigated the absolute differential between peak and trough revenues.
Early reports great – Ichor is Punxsutawney Phil that throws no shade
Ichor, one of our favorite sub suppliers to the industry, just pre-announced a great Q4 and an excellent Q1 guide. This obviously bodes very well for both Lam and Applied the two biggest customers of Ichor.
Its not hard to extrapolate that Lam and Applied should have equally great reports – driven by both TSMC and the start of Samsung spend.
Ichor, being a sub-supplier in a cyclical industry is obviously highly levered to the cyclicality and will see even more leverage to the upside than their customers.
The company management has done a great job of acquisitions throughout the cycle and will likely see full benefit in the coming upcycle.  It also takes keen management to navigate the downcycle as well as Ichor has, and they have down a great job managing costs and Ichor is clearly a harbinger of good things coming to the industry.
The stocks
Lam and Applied (and of course Ichor) could easily be bought from the Ichor news.  We would also suggest MKS and AEIS as well as UCTT. Right now the news out of Q4 wiil be very good with Q1 outlook equally good so we see reduced downside in the near term for most of the stocks.
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The Tech Week that was January 6-10 2020

The Tech Week that was January 6-10 2020
by Mark Dyson on 01-13-2020 at 6:00 am
Categories: China, Foundries, TSMC

Semiconductor Weekly Summary

Happy New Year to everyone.. lets hope 2020 is a great year.. The indicators are all pointing in the right direction but it will not take much to derail it if external factors change. Here is my weekly summary of all the important news from the semiconductor industry around the world.

2020 is starting very differently from 2019 with much optimism around. This article in Semiconductor Engineering surveys CEO’s across the industry to get their views on 2020. 5G, AI and big data are all factors that should be big this year and help drive the recovery.

CES was held last week with many new consumer ideas on display. Smart homes was certainly one of the hot topics with smart speakers for the shower, smart frying pans that weight your food and smart cooker hobs that you can control by voice, smart shelves for monitoring your groceries amongst some of the items on display. One item that would certainly be useful in Singapore was a device that instantly cools the object placed in it, like a reverse microwave, it can cool a can of beer in 2minutes. 8K TV’s were on display as were foldable computers, and of course there were lots of robots and AI applications. Here are some articles about the technology on display in the show. An overview from the BBC, the standout gadgets by the Guardian, the key takeaways by the Verge.

The Taiwan foundries ended the year on a high. TSMC hit another record high for the quarter, the second successive quarter it achieved this. Q4 revenue was US$10.5billion, up 8% sequentially. December revenues were down 4% sequentially at US$3.44billion but was up 15% on a year ago.

UMC saw revenues surge in December up 17.4% from a year ago, reporting revenues of US$445million. Q4 revenues were also up 17.4% on a year ago, mainly due to the additional revenues from the taking full control of Mie Fujitsu foundry in Japan.

Specialty foundry Vanguard (VIS) didn’t fair quite so well in Q4, reporting Q4 revenues were down 2.2% on year ago at US$87million.

For the back end assembly test provider ASE reported Q4 revenue up 8.9% YoY at US$2.27billion and up 4.1% sequentially for the ATM group. December revenue was up 2.5% on November with revenue of US$771million, this was up 16% on a year ago.

Market research company IC Insights reported that the pure play foundry market decreased 2% globally in 2019 compared to a year ago. China was the only region to see an increase in pure play foundry market last year growing 6%. Taiwan foundry TSMC reported that approx. 25% of it’s customers were in China.

One of the side effects of trade wars is that it prompts countries to become more self sufficient. As a result of the trade war between South Korea and Japan, South Korea has announced Dupont will invest $28million in South Korea to develop advanced photoresists and other materials by 2021 to allow South Korea to be less dependent on Japan supplies.

Similarly in China, China is pushing to decouple it’s technology from the US as a result of the US-China trade war which has lead to a boom for some Chinese tech companies.

It appears that the US put a lot of pressure on the Netherlands to prevent ASML from delivering a EUV lithography tool to China and to cancel the sale.

Despite the trade war and the ban on Huawei, Huawei still managed to grow it’s revenue in 2019 by 18% to US$121.7billion, though this was lower than originally predicted due to the trade war preventing the company access to source parts. Huawei said that 2020 will be a difficult year and it will not be able to grow as fast and only grow by 3.9%.

It is reported that production was impacted at its Samsung Electronics Hwaseong plant due to a minute long power blackout. It is speculated that the incident caused million of dollars in losses.

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Semiconductor Review 2019 into 2020!

Semiconductor Review 2019 into 2020!
by Daniel Nenni on 01-03-2020 at 6:00 am
Categories: China, Foundries, TSMC

CES 2020

Semiconductors continue to surge and lead technology sectors all over the world. TSMC has always been my economic bellwether and 2019 was another great year as the TSM share price almost doubled. But it looks like the best is yet to come with TSMC significantly increasing CAPEX to cover 7nm and 5nm demand.

TSMC CEO C.C. Wei increased 2019 CAPEX from $10.5B in 2018 to more than $14B in 2019 with a big Q4 spend. Remember, TSMC builds capacity based on customer orders and not a dart board forecasting. With TSMC winning both the 7nm and 5nm popular vote, 2020 should be another blockbuster CAPEX year to backfill demand.

There are two VERY disruptive semiconductor trends to watch in the next year or three and that is the large systems companies taking control of their silicon (including Google, Facebook, Amazon, Microsoft, etc…) and China also taking control of their silicon.

Apple started it and now all systems companies in competitive markets will follow. It will be interesting to see who the big players are at CES 2020 next week and more importantly how many of them are making their own chips. My bet would be the majority of them including the automakers. It’s not really a fair bet since SemiWiki.com is the leading semiconductor design enablement portal with more than 3.25 million unique views and we get to see who reads what, when, and where they are from.

Why are systems companies dominating semiconductor design? Because they can use prototyping and emulation to get a jump on verification and software development and really tune the silicon to the system. Systems companies are also VERY competitive and can write some VERY big checks and they will not miss tape-outs or product ship dates. This is so un-fabless-like it isn’t even funny. It really is a new semiconductor world order.

Speaking of a new world order, China is also disrupting the semiconductor industry with billions of dollars invested in the “Made in China 2025” semiconductor supply chain initiative.

Think about it, China consumes more than 50% of semiconductor production worldwide and they only produce about 20% of said chips. My guess is 2020 and 2021 will see unprecedented China chip manufacturing growth due to increased memory (DRAM and NAND) manufacturing capacity coming online. Add in the political turmoil motivator and memory hogging mobile, 5G and AI, the Made in China 2025 initiative will get a major boost, my opinion.

I will be in China again this month and am excited to see what’s new. You can Google around all you want but there is nothing like being there.

2019 was also a big year for SemiWiki.com. We unleashed SemiWiki 2.0 in June with many new cloud-based features and more to come. Traffic and member registration is again growing double digits and we are already working on SemiWiki 3.0.

I would truly like to thank all of our bloggers, partners, readers, and registered members for your continued support. SemiWiki has been an exciting 10 year adventure and I’m looking forward to working with you all in the coming years. After spending my entire 35+ year career in semiconductors I can say that without a doubt the best is yet to come, absolutely!

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ANSYS, TSMC Document Thermal Reliability Guidelines

ANSYS, TSMC Document Thermal Reliability Guidelines
by Bernard Murphy on 01-01-2020 at 6:00 am
Categories: 5G, Ansys, Inc., EDA, FinFET, Foundries, TSMC

Automotive Reliability Guide min

Advanced IC technologies, 5nm and 7nm FinFET design and stacked packaging, are enabling massive levels of integration of super-fast circuits. These in turn enable much of the exciting new technology we hear so much about: mobile gaming and ultra-high definition mobile video through enhanced mobile broadband in 5G, which requires support for millimeter wave frequencies; high-speed networking in hyperscalar datacenters through 100G connectivity; blazing fast AI accelerators in those same datacenters; and fusion of multiple sensor sources to build environment-aware intelligence for automotive safety and autonomy, building security, autonomous drones and many more capabilities.

With new technologies we always find new challenges. ANSYS and others have been hearing from chip and system builders supporting these domains that they are seeing increasing post-silicon failures in the devices they are building. These devices are nominally perfectly fine, pass standard testing, but fail in system operation primarily related to voltage, timing and process variations. Tianhao Zhang  (Dir. Foundry Relations at ANSYS) says that between what they are hearing from customers and industry reviews, 75% of these product failures can be attributed to thermal or vibration effects.

Thermal also increases cost through need for more advanced cooling, it reduces performance through increased resistance in the interconnect and degraded transistor performance and it increases noise leading to random failures. It also decreases reliability, on chip through electromigration and device aging, and in the package and system through mechanical stress during to warping.

This is not a problem that can be dealt with later. One chip design VP has said that self-heating (related to FinFETs) and thermal analysis are now absolute requirements for automotive and high-performance computing applications. Another noted that compared to planar designs they are now seeing temperature increases in metal of 10 to 20 degrees, and that is making design for reliability much more challenging.

TSMC has been hearing all the same issues and has been increasing the number of checks they require, particularly thermal checks, to offset these types of problem. TSMC has worked closely with ANSYS to prove and document a thermal solution they jointly support. This includes an ANSYS reference flow for transistor, chip and package/3D-IC levels, from 20nm down to 5nm. These can be downloaded from the TSMC portal.

They are also working together on solution guides for specific application flows. For example, ANSYS now provides solution guides for automotive development on 16nm and 7nm. These cover electromigration, thermal and ESD topics. In the thermal analysis section, the document details multiple areas including the flow, and also provides test cases and case studies.

The ANSYS analysis is not based on a simple averaging of thermal effects. They analyze all the way down to the physical implementation of transistors and interconnect systems under representative activity scenarios, to estimate local heating, interconnect heating and heat dissipation. They do this using analytics from RedHawk, together with finite-element analysis applied at the die, stacked die, package and board level. And they’re computing temperature profile by looking at (thermal) conduction, radiation and convection flows, the last of these though detailed fluidics analysis. This is a true bottoms-up multi-physics solution. You can learn more in THIS WEBINAR, presented by Tianhao and Karthik Srinivasan (Sr Prod Mgr at ANSYS).

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TSMC, Huawei, the US Government, and China

TSMC, Huawei, the US Government, and China
by Daniel Nenni on 12-30-2019 at 6:00 am
Categories: China, Foundries, Samsung Foundry, TSMC
2 Comments

Morris Chang TSMC

The media is trying to disparage the semiconductor industry again. It’s hard to not take this type of desperate journalism personal. Semiconductor people are the smartest and hardest working people in the world and we deserve better, absolutely.

Morris and Sophie Chang TSMC

TSMC founder sees trade dispute as ‘reality show with no script’ July 2018

The latest media scam is that the US Government is pressuring TSMC about stopping wafer shipments to Huawei (HiSilicon). The Financial Times started it with “US urges Taiwan to curb chip exports to China” and the cut/paste media sites jumped all over it and “made it their own”.

TSMC responded with:

“We did not have any discussion with either the Taiwan or the U.S. governments regarding shipping wafers to HiSilicon, nor have we received any instruction from either government not to make the shipments,” TSMC spokesperson Elizabeth Sun told Caixin in an email, adding that it will continue shipments while complying with trade regulations.

Remember, TSMC has two fabs in China and plenty of room for expansion. The US accounts for 61% of TSMC’s revenue and China is a growing 17%. Taiwan is 8%, Japan 6% and others are 1%. The question is: What would happen if TSMC cut wafer shipments to the US or China? Answer: The end of modern life as we now know it.

Another ignorant quote:

“Last month, a U.S. official informed Taiwanese diplomats that the semiconductors produced by TSMC and then procured by Huawei, were ending up in Chinese missile guidance systems aimed at Taiwan, as per the reporting by Financial Times.”

I can assure you TSMC knows more about what their customers are doing than politicians in any country including Taiwan. There are very few secrets inside the fabless semiconductor ecosystem and TSMC knows more than most. And does it really matter who made what, when, and where in the case of war? It doesn’t matter because there is nothing you can do about it. That ship sailed a long time ago.

Bottom line: TSMC is the new Switzerland and has the full support of the US, Taiwan, and China Governments.

Another interesting headline:

“Samsung is pouring $116 billion towards beating TSMC in the race to 5nm and beyond”

First and foremost, TSMC has already won the race to 5nm and EUV if the finish line is high volume manufacturing versus press releases or “leaked” road maps.

In order for Apple to ship millions of iProducts in Q4 2020 the 5nm EUV process must be frozen by the end of 2019 starting production in Q1 2020. In fact, TSMC recently outlined their 5nm process at IEDM.

I remember when SMIC launched in 2000 and suggested that they would compete with TSMC. It was believable to me because the China Government was strongly behind them and the China consumer market was theirs for the taking. Unfortunately, competing with TSMC proved too hard for SMIC who then resorted to stealing trade secrets. The resulting litigation cost SMIC hundreds of millions of dollars and 10% of their stock.

To say that SMIC is a trailing edge foundry is quite generous. SMIC has just now released a 14nm process four years after TSMC who is now at 5nm with full EUV. SMIC doesn’t even have an EUV machine yet and they may not get one if the current political turmoil is not properly addressed.

According to reports, the SMIC 14nm was co-developed with Qualcomm who also worked with TSMC and Samsung on 14/16nm processes. I’m sure the TSMC and Samsung legal staff already have SMIC 14nm die under review.

GlobalFoundries also had their sites set on competing with TSMC but that never really happened, not even close.

Samsung officially became a pure-play foundry in 2017 when they reorganized all of their logic fabs under Samsung Foundry. Samsung Electronics is Samsung Foundry’s biggest customer of course but they do have a long history of external foundry business. Apple was the big start with the introduction of the iProducts and other big fabless companies (Qualcomm) have followed.

Samsung certainly is a leader in connectivity and IoT now that all Samsung appliances, TVs, and other electronic gadgets have WiFi so they can talk to you throughout the day. You should see the Samsung booth at CES. It’s more of a connected city than a trade show booth but I digress.

Bottom line: While Samsung’s “pouring $116 billion towards beating TSMC” is impressive you have to understand that the TSMC ecosystem of partners and customers have poured trillions of dollars into TSMC staying ahead of all foundry comers, right?