Posted on

TSMC to Build first US Fab in Arizona!

TSMC to Build first US Fab in Arizona!
by Daniel Nenni on 11-15-2020 at 10:00 am
Categories: Foundries, TSMC
9 Comments

TSMC North America SemiWiki

Well, it’s official, the TSMC Board of Directors approved an investment to establish a wholly-owned subsidiary in Arizona with a paid-in capital of $3.5 billion. As history shows the investment may be more than that but $3.5B is a great starting point. This is being discussed in the SemiWiki Forum  and I have been gathering inside intelligence from the ecosystem so let me offer my experience, observation, and opinion.

This is a GREAT political move by TSMC that will help insure the independence of Taiwan, absolutely. It’s only 20,000 wafers per month to start but it can be expanded quite rapidly as TSMC expertly does. Consider this first fab a “toe in the water” test to see how the US Government responds.

In my opinion the target customers would be the US Government and suppliers. Xilinx for example does quite a bit of government business with their FPGAs. Intel is shipping 16nm products today so a US based 5nm fab in 2024 would be perfect timing for Xilinx “made in the USA” customers.

And yes I know that TSMC built a fab (WaferTech) in the United States in 1996 but that was a joint partnership with three other companies. TSMC bought out the partners and now runs it as a wholly owned subsidiary.

Unfortunately, this “toe in water” move is certainly not a guarantee of political success. TSMC did a similar toe in water test in China with Fab 16 in Nanjing (2016) which did not go as planned. Rumor has it the China Government took this olive branch and used it to advance the China semiconductor initiative by “monitoring” construction and recruiting TSMC employees:

China hires over 100 TSMC engineers in push for chip leadership, Emerging chipmakers offer lavish pay packages to snap up talent.

TSMC also has an older 200mm fab in Shanghai but competing against the China Government backed SMIC is now rather challenging for foreign owned manufacturing companies inside of China.

The ultimate goal of course is for TSMC to be an active part of the H.R.7178 – CHIPS for America Act introduced in Congress on June 11th, 2020. Given the importance of semiconductors to modern life let’s hope this bill passes and ushers in a new era of global semiconductor collaboration, absolutely.

Creating Helpful Incentives to Produce Semiconductors for America Act or the CHIPS for America Act

This bill establishes investments and incentives to support U.S. semiconductor manufacturing, research and development, and supply chain security.

Specifically, the bill provides an income tax credit for semiconductor equipment or manufacturing facility investment through 2026. The bill also establishes a trust fund to be allocated upon reaching an agreement with foreign government partners to promote (1) consistency in policies related to microelectronics, (2) transparency in microelectronic supply chains, and (3) alignment in policies towards nonmarket economies.

The Department of Commerce shall, through the National Institute of Standards and Technology (NIST), carry out a program of research and development investment to accelerate the design, development, and manufacturability of next generation microelectronics, including through the creation of a Manufacturing USA institute for semiconductor manufacturing. Commerce shall also establish a program to match state and local government incentives offered to private entities for the purposes of building fabrication facilities relating to semiconductor manufacturing. Further, Commerce shall assess the capabilities of the U.S. industrial base to support the national defense in light of the global nature of supply chains and interdependencies between the industrial bases of the U.S. and foreign countries with respect to the manufacture and design of semiconductors.

The Department of Defense shall prioritize the use of specified available amounts for programs, projects, and activities in connection with semiconductor and related technologies.

The President shall establish within NIST a subcommittee on matters relating to U.S. leadership in semiconductor technology and innovation, which shall develop a national strategy on semiconductor research.

“Semiconductors were invented in America and U.S. companies still lead the world in chip technology today, but as a result of substantial government investments from global competitors, the U.S today accounts for only 12 percent of global semiconductor manufacturing capacity,” said Keith Jackson, President, CEO, and Director of ON Semiconductor and 2020 SIA chair. “The CHIPS for America Act would help our country rise to this challenge, invest in semiconductor manufacturing and research, and remain the world leader in chip technology, which is strategically important to our economy and national security. We applaud the bipartisan group of leaders in Congress for introducing this bill and urge Congress to pass bipartisan legislation that strengthens U.S. semiconductor manufacturing and research.”

Posted on

AMD and Intel Update with Xilinx

AMD and Intel Update with Xilinx
by Daniel Nenni on 11-06-2020 at 10:00 am
Categories: FPGA, Intel Foundry, TSMC, Xilinx
5 Comments

AMD Xilinx Acquisition

The AMD acquisition of Xilinx is certainly big news but as an insider looking at the media coverage I think there are a few more points to consider. While most of the coverage has been positive there will always be negatives and we can look at that as well.

Intel acquired Altera in 2015 for $16.7B at a 50% premium which was a major disruption for the FPGA industry. Altera and Xilinx were in a heated battle for manufacturing supremacy when Xilinx joined Altera at TSMC for 28nm and beat Altera to first Silicon. Altera responded by moving manufacturing to Intel at 14nm which resulted in Intel acquiring Altera. Looking back, it was a great move which provided Intel with a larger cloud footprint. Rumors of a Xilinx acquisition swirled afterwards but a 50%+ price premium was expected and the motivation on either side was not strong enough.

AMD and Intel are also in a heated battle for manufacturing supremacy. With AMD’s move to TSMC at 7nm the battle has shifted in AMD’s favor. Based on the latest investor calls AMD is in a very strong position against Intel for 7nm and 5nm products. Xilinx also reported a great quarter with beats at the top and bottom line with the Data Center Group hitting record revenue, up 23% Q/Q and logging 30% annual growth. This is another one of those 1+1=3 acquisitions.

And for those naysayers who think AMD will abandon the mainstream FPGA market there really is a simple solution: Keep Xilinx as a separate business unit, FPGA business as usual but also as a leverage for AMD chip business and vise versa.

The other negative I heard is that AMD and Xilinx will be fighting for leading edge wafers which is not true. Xilinx designs leading edge products but it takes time for Xilinx customers to get systems developed, qualified and shipped in volumes. Xilinx stayed on 28nm for the longest time and the new Xilinx Vertex Ultrascale+ products utilize 14/16nm process technology.

From the CEOs:

“Our acquisition of Xilinx marks the next leg in our journey to establish AMD as the industry’s high performance computing leader and partner of choice for the largest and most important technology companies in the world,” says AMD President and CEO Dr. Lisa Su in a press release.

“This is truly a compelling combination that will create significant value for all stakeholders, including AMD and Xilinx shareholders who will benefit from the future growth and upside potential of the combined company. The Xilinx team is one of the strongest in the industry and we are thrilled to welcome them to the AMD family.”

“We are excited to join the AMD family. Our shared cultures of innovation, excellence and collaboration make this an ideal combination. Together, we will lead the new era of high performance and adaptive computing,” adds Victor Peng, Xilinx president and CEO.

“Our leading FPGAs, Adaptive SoCs, accelerator and SmartNIC solutions enable innovation from the cloud, to the edge and end devices. We empower our customers to deploy differentiated platforms to market faster, and with optimal efficiency and performance. Joining together with AMD will help accelerate growth in our data center business and enable us to pursue a broader customer base across more markets.”

Sounds good to me. Now let’s talk about the other insider synergies. First and foremost is the Xilinx – TSMC relationship. The Xilinx foundry group is one of the best I have seen. I’m not saying AMD has a bad foundry group, but Xilinx has been with TSMC since 28nm and has been first to silicon on each and every node since. There is only upside for AMD here. And this includes packaging. Remember, Xilinx is a close packaging partner with TSMC (CoWoS).

Another interesting synergy is company culture. Since the beginning of AMD their marketing has outpaced engineering. Blame Jerry Sanders (AMD’s founding CEO and showman extraordinaire).  Thankfully, Lisa Su embraced that culture and brought products to market that now more evenly pace marketing.

With Xilinx, on the other hand, engineering always outpaced marketing. We included a chapter on the history of Xilinx in our first book “Fabless: The Transformation of the Semiconductor Industry” as they were one of the first fabless companies. This engineering centric culture is a biproduct of highly technical CEOs of course.

If Lisa Su is able to combine the two cultures it will be a big part of the 1+1=3 acquisition equation for sure.

Another interesting question, what is next for the FPGA industry? Programmability has never been a more critical part of the semiconductor industry as a whole. In my opinion another acquisition is looming. No, not Lattice semiconductor or Microchip. I see Achronix as being the next hot FPGA property and hopefully Nvidia has enough money left after acquiring Arm. Achronix is a $200M or so 150+ person company that is located conveniently close to Nvidia. If you combine their speedy high capacity FPGAs with the Nvidia AI/HPC software ecosystem it will be a 1+1=300 acquisition, absolutely.

Posted on

Leading Edge Foundry Wafer Prices

Leading Edge Foundry Wafer Prices
by Scotten Jones on 11-06-2020 at 6:00 am
Categories: Semiconductor Services, TechInsights, TSMC
8 Comments

Slide1

I have seen several articles recently discussing foundry wafer selling prices for leading edge wafers, these articles all quote estimates from a paper by the Center for Security and Emerging Technology (CSET). The paper is available here.

My company IC Knowledge LLC is the world leader in cost and price modeling of semiconductors and MEMS. We have been selling commercial cost and price models for over twenty years and our customer base is a who’s who of system companies, fabless, foundries and IDMs, OEMS, materials companies and analysts. I thought it would be interesting to examine how the estimates in the paper were produced and how realistic they are.

Capital Costs

CSET begins their analysis looking at TSMC’s financial releases and find from 2004 to 2018 that revenue can be broken down into 24.93% depreciation, 36.16% other costs and 35.91% operating profit. They also come up with a 25.29% capital depreciation rate. They then go on to calculate capital consumed per wafer and then use these percentages to infer other costs. I see a couple of problems with this approach, one, it assumes these ratios are the same for all nodes, they aren’t, and two, the depreciation rate makes no sense as I will explore further below.

The capital consumed calculation is as follows:

“To obtain capital consumed per wafer, we first calculate capital investment per wafer processed per year. TSMC currently operates three GigaFabs (Fabs 12, 14, and 15) with a fourth (Fab 18) scheduled to come online in 2020 with expansion thereafter.”

This ignores TSMC’s Fab 16 with two phases in China.

“These four fabs include a total of 23 fab locations each with a known initial capital investment in 2020 USD— representing investments in facilities, clean rooms, and purchase of SME—and annual 300 mm wafer processing capacity.”

Fabs 12, 14 and 15 are each 7 phases, Fab 18 is planned to be 6 phases, apparently they are considering the 21 phases from Fabs 12, 14, and 15 plus 2 phases from Fab 18 that have recently come on-line and ignoring Fab 16 (although Fab 16 is relatively small and therefore less significant than the GigaFabs).

They plot capital investment per 300mm wafer processed per year and fit an exponential trend line to the plot.

I do not know what their specific data source is, TSMC sometimes announces fab capacity and initial investment but not always and these are often more aspirational numbers than actual costs. These fabs also often have an initial cleanroom build and then are equipped over time as they are ramped up with ramps covering more than one year. The ultimate fab capacity is often the result of additional investments. It is not clear to me how this becomes a cost per wafer per year with this approach. These values eventually get converted to capital investment per wafer per year by node based on the year and quarter each node was introduced and then assuming the capital investment per wafer by year represents that node. The problem is TSMC is not always only ramping one node in any given year plus the other issues discussed above.

The way we address capital cost in our models is fundamentally different and more detailed.

  1. For each node we built a representative process flow, this is done based on our own experience, consultation with industry experts, conference papers, patents, and actual construction analysis from our strategic partner TechInsights.
  2. We maintain a database of every 300mm wafer fab in the world tracking the initial and all upgrade states. This database is a combination of public and private sources.
  3. We maintain a database of equipment throughput, cost and footprint by node and wafer size. Once again this is based on public and private sources. Our Strategic Cost and Price Model is in use at all the major equipment OEMs and we have an extensive network of sources for this information.
  4. For each 300mm fab we calculate a fab size and cost and equipment set based on the specifics of the process, and the fab states. We calculate this for the initial fab state and up to twelve upgrades or expansions per fab.

With the amount of information going into these calculations and the complex methods used we need to validate our methods. Around 2000 – 300mm fab began to come on-line and quickly accounted for most of the capital spending at all the major semiconductor companies. For TSMC as an example, we have taken their publicly disclosed capital spending each year since 2000 and plotted it versus year as a cumulative number. We have then modeled all their 300mm fabs and spending by fab by year and added that up to create a cumulative plot. After accounting for some residual 200mm spending in the early years and any spending not yet on-line (our spending calculations are based on on-line dates) we get the following plot.

Figure 1. TSMC calculated versus actual cumulative capital spending.

 The resulting plot shows excellent match. We have done this same analysis for Samsung, Intel, Micron Technology and many others with equally good correlation.

TSMC typically focuses a fab on a single node so we now have capital costs per wafer-out estimates by node. Comparing our estimates by node to the estimates in row 2 of table 9 in the CSET paper we find that at the 90nm node the values are similar, but they steadily diverge as the nodes get smaller.

In the CSET paper rows 3 and 4 provide a net capital depreciated and undepreciated capital at the start of 2020 that are then used with a 25.29% depreciation rate to get the capital consumed per wafer value presented in row 5. This whole calculation makes no sense to me. TSMC has disclosed they use 5-year straight-line depreciation for equipment and 10-year straight-line for facilities. What this means is that if you put a piece of equipment on-line you write-off 20% of the equipment investment each year for the first 5 years and then the depreciation goes to zero in year 6. For facilities you write-off 10% of the value each year for 10 years and then the depreciation goes to zero. 90nm in 2020 is fully depreciated and even brand new 5nm investment is only depreciating at something less than 20% after blending equipment and facility depreciation.

Applying five-year straight-line for equipment, equipment installation and automation and ten-year straight-line depreciation to facilities values from our calculation we get the following depreciation by node plot. Also, on the plot is TSMC’s reported depreciation and as in the previous figure you can see the match is excellent.

Figure 2. TSMC calculated depreciation by node and quarter versus TSMC reported depreciation.

Based on these plots and other comparisons we have made it is clear our capital calculations are highly accurate.

Other Costs and Markup

This bring us to the other elements that add up to revenue.

First, to complete the wafer cost calculation:

  1. Starting Wafer – starting wafers are purchased from wafer suppliers and we have contacts at wafer brokers and wafer suppliers who provide us with the open market pricing.
  2. Labor – we have an extensive database of direct and indirect labor rates by country and year built up from a network of private and public sources.
  3. Equipment maintenance – we use a percentage of the capital investment in equipment to estimate the equipment maintenance cost. The percentage varies depending on wafer size and product type being made in the fab, for example memory is different than logic.
  4. Facilities – we do detailed facilities operating cost calculation accounting for electric and natural gas rates by country and year and equipment requirements, ultrapure water cost, waste disposal, facilities maintenance, insurance costs, and more. Once again, we have public and private data sources.
  5. Consumables – based on the process flow we calculate the usage of hundreds of individual consumables and combing that with a database of cost by consumable and year calculate the total consumable costs. We get consumable usage and cost data from our strategic partner Linx Consulting as well as an extensive network of materials suppliers.

The summation of these values and the depreciation results in manufacturing costs per node.

To get to selling price, a gross margin must be applied where the gross margin includes Selling, General and Administrative Costs (SG&A), Research and Development Costs (R&D) and Operating Profit. TSMC discloses average gross margin in their filings, however gross margin is not flat across their product line (it also varies with fab utilization). When a new process comes on-line, depreciation costs are high but then as the equipment becomes fully depreciated the wafer manufacturing costs drops more than in-half. TSMC and other foundries typically do not pass all the cost reduction that occurs when equipment becomes fully depreciated on to the customer, the net result is that gross margins are lower for newer processes and higher for older fully depreciated processes. We account for this in our calculation, but once again the calculation disclosed in CSET the paper assumes the other wafer costs and gross margin are consistent from node to node.

In our case we have a variety of ways to check our wafer prices including customers who buy wafers and compare them to our calculations, and our ability to use proprietary methods to compare our results to company filings. For example, we have compared our calculated results to TSMC’s filings every quarter from Q1-2000 to Q2-2020 with excellent match every quarter.

This brings us to the key question, how accurate are the row 7 “Foundry sale price per wafer” values in the paper and the answer is not very. There is basically an error slope to the results with the 90nm prices being too low and at 5nm the prices are too high.

Conclusion

Although the value in the CSET are not off by an order of magnitude, they are off. I have customers frequently ask me for rules of thumb and I tell them my rule of thumb is that all rules of thumb are wrong.  Accurate estimates of wafer manufacturing costs and selling prices require detailed calculations such as are embodied in our commercial cost and price models. We currently offer five cost and price models targeting different segments of the semiconductor and MEMS industries.

For more information on our models please go to www.icknowledge.com

Also Read:

VLSI Symposium 2020 – Imec Monolithic CFET

SEMICON West – Applied Materials Selective Gap Fill Announcement

Imec Technology Forum and ASML

Posted on

Are TSMC and Intel Partnering in Arizona?

Are TSMC and Intel Partnering in Arizona?
by Daniel Nenni on 11-01-2020 at 10:00 am
Categories: Foundries, Intel Foundry, TSMC
2 Comments

TSMC Career Opporunitites

After months of back and forth TSMC finally announced plans to build a fab in Arizona. The announcement was not made in the press or on the most recent investor call but on LinkedIn. A sign of the times I guess but since they need to hire a bunch of semiconductor people it was more than appropriate.

“We’re delighted to catch up with you that TSMC had announced its intention to build and operate an advanced semiconductor fab in Arizona. This U.S. advanced foundry fab not only enables us to better support our customers and partners, we also wish to attract global talents to work with us to change the world.At TSMC, we are working consistently to provide the most advanced technologies to enrich human life. Join us to initiate and witness the new semiconductor era with remarkable people around the world. https://lnkd.in/gX-aEre”

The question is why? TSMC can build fabs in partnership with the Taiwanese Government for pennies on the dollar which is in fact one of the reasons why TSMC is the dominant semiconductor foundry. TSMC did build a leading edge fab in China to better relations with the Chinese Government but spying was a serious problem so TSMC has slowed that effort and now has extensive security protocols in place which is for the greater good of TSMC, absolutely.

One rumor is that TSMC is working with the Federal and State Government to better secure the semiconductor supply chain in the United States. The US Government is finally putting up some money to offset costs of semiconductor manufacturing in the US. Let’s not forget that manufacturing started here but was shooed away by the EPA about the time I started in semiconductors in the 1980s.

U.S. lawmakers propose $22.8 billion in aid to semiconductor industry

Another rumor, which I may have just started, is that TSMC and Intel are already working together in Arizona. Arizona is Intel’s home court so is it a coincidence that TSMC is landing there? Another coincidence, Intel is discussing outsourcing designs to a foundry, a decision to be made by the end of the year according to Intel CEO Bob Swan. I’m sorry but I really don’t believe in coincidence especially when it comes to TSMC. TSMC management is the best this industry has seen in decades so this storyline is all about TSMC.

Another rumor is that Samsung is in the running for the Intel outsourcing gig which was fortified by an Intel executive giving a keynote at the Samsung Foundry day last week. Or maybe that was just part of what Bob Swan said about Intel working closer with the semiconductor ecosystem? Personally I think it was a bad move by Intel to keep TSMC on its toes in the outsourcing discussions. Given AMD’s recent moves, TSMC holds all of the outsourcing cards so Intel should keep this negotiation at the utmost professional level, my opinion.

This reminds me of the head-to-head foundry battle between Altera and Xilinx. In the FPGA business the first to silicon got a market share boost. Altera was partnered with TSMC and Xilinx UMC. Xilinx actually had a dedicated floor in the UMC Hsinchu HQ. At 40nm UMC fell behind so Xilinx jumped to TSMC and actually beat Altera to 28nm. The rest is history but Xilinx beat Altera to first silicon from that day forward and now dominates the $5B+ FPGA market. AMD acquiring Xilinx makes this even more interesting. I will write more about that later because it is a great move by AMD.

Bottom line: To better compete with AMD, Intel will have to closely partner with TSMC like Xilinx did. Just my opinion of course but who would know better than me?

 

 

 

Posted on

Intel TSMC Update!

Intel TSMC Update!
by Daniel Nenni on 10-23-2020 at 10:00 am
Categories: Foundries, Intel Foundry, TSMC
15 Comments

Intel Bob Swan TSMC SemiWiki 1

Based on the Intel investor call yesterday here are some interesting comments Bob Swan made related to Intel outsourcing manufacturing and 7nm progress. Let’s start with the prepared statement:

Bob Swan: “Over the last couple of years, we have been focused on three critical priorities; improving our execution to strengthen our core business, extending our reach to accelerate the growth of the company, and continuing to thoughtfully deploy your capital.

We have and do get great benefits from internal manufacturing. We call it our IDM advantage, because it provides us attractive economics, co-optimization of design and process technology development and supply assurance. So as we engage the ecosystem more broadly, we want to preserve some of the advantages of IDM like schedule, performance and supply, as we work with our strategic partners.

Finally, I want to reiterate our intention to continue investing in leading process technology development to bring future process nodes and advanced packaging capabilities to market. This is a powerful force in creating future differentiation for our products and provides tremendous option value for our business.”

Me: Clearly Bob has been getting grief about his previous comments on outsourcing to pure-play foundries. There has also been speculation about Intel outsourcing to both TSMC and Samsung which fanned the “Intel will go fabless” flames even further.

As I previously stated in Three Things You Have Wrong About Intel: “The one thing Bob Swan will NOT do however is erase the Intel manufacturing legacy and go fabless. Nobody wants that on their semiconductor CEO resume.”

I also find zero truth in the rumor that Intel will use both TSMC and Samsung. To be successful in outsourcing and competing with AMD on a level playing field Intel needs to be exclusive with TSMC. If you outsource to both TSMC and Samsung you will be on the outside looking in, absolutely.

During the Q&A:

“Can you explain how easy it is to transition from TSMC back to your internal manufacturing? How comfortable that is? And would that be for existing type of architecture or more like chiplet type of architectures?“

Bob Swan: “Yes. It’s a good question. I mean I gave kind of the criteria around should we under what circumstances go out more of schedule predictability performance and of economics if you will the bookend on that — on those three criteria really around one, the ease of portability of our technologies to go out. And I would say, we feel very confident in the ability of us being able to port to TSMC.

And the other bookend is in the event that we go out what’s the ease in which we can port back if we conclude that’s the best alternative for either core products or chiplets. I would just say that we feel increasingly confident that yes in fact, if we conclude going out makes sense that we can. And also that in the event we want to port back in, we can as well. And that’s — those are general observations around the bookend questions.”

Me: Hopefully this is based on Bob’s semiconductor terminology naivety. If Intel does in fact “port” designs over to TSMC they will be less competitive than AMD’s direct designs to TSMC in regards to power, performance, and area. Let’s not forget what happened when Apple ported the A9 from Samsung 14nm to TSMC 16nm (ChipGate). It is progress however for Bob to acknowledge they are in fact working with TSMC.

Quick 7nm Update:

Bob Swan: “I would say since the last time we spoke, our 7-nanometer process is doing very well. I mean, last time we spoke we had identified an excursion. We had root caused it. We thought we knew the fix. Now, we’ve deployed the fix and made wonderful progress. But nonetheless, we’re still going to evaluate third-party foundry versus our foundry across those three criteria. And the call will be towards the end of this year early next year.“

Me: I know that Intel has TSMC PDKs but I have not confirmed any tape-outs as of yet. I do think that Intel will outsource price and power sensitive chips to TSMC to better compete in those markets and to reduce manufacturing expenses. Today Intel has three fabs running 10nm chips. If they do partner with TSMC Intel will only need one 7nm fab which is a very attractive CAPEX reduction (fablite versus fabless) while preserving their IDM status.

Posted on

TSMC Sets the Stage for a Great 2021!

TSMC Sets the Stage for a Great 2021!
by Daniel Nenni on 10-16-2020 at 10:00 am
Categories: FinFET, Foundries, TSMC
5 Comments

TSMC Revenue Analysis 2020

TSMC is the bellwether for not just the semiconductor industry but the worldwide economy. TSMC makes semiconductors, semiconductors are where electronics begin and electronics are the foundation of modern life, absolutely.

Apple is also a key economic indicator and as we all know Apple is a strategic partner of TSMC. The Apple TSMC relationship started with the iPhone 6 and other iProducts (20nm in 2014) and continues to this day. The recently introduced iPhone 12 is based on TSMC 5nm. Next year Apple will use an enhanced version of 5nm and in 2022 it will be 3nm.

TSMC raised its 2020 revenue forecast for a second time this year (10% -> 20% -> 30%) with strong demand for 5G and high-performance computing (HPC). The pandemic has resulted in a much stronger emphasis on mobile and cloud computing which should continue in Q4. IoT is also up but Automotive and DCE is down, again due largely to the pandemic. TSMC’s HPC (cloud) content will also benefit from additional AMD and Intel wafer agreements from 7nm down to 3nm over the next five years.

TSMC Revenue Analysis:

In my opinion AI and the cloud will be the key semiconductor drivers moving forward. Vast amounts of data is being generated by our electronic devices. The data is now moving to the cloud for harvesting and monetization. Cars are an easy example. I can assure you that Tesla will be using data from their cars to make more money than from the selling the cars. Think Google and search, Facebook and personal information, or Amazon and shopping, it is all about the data.

It’s interesting to note the process node breakout:
38% of revenue is from mature CMOS nodes. Those nodes were cloned by UMC, SMIC, and GLOBALFOUNDRIES so there is strong competition where designs can be moved from one fab to another with relative ease. That is not the case with FinFET based designs so TSMC’s strong market position will continue to evolve in the future.

For 20nm and 10nm Apple was the only customer to hit HVM thus the shrinkage. TSMC moved 20nm fabs to 16nm and 12nm. The 10nm fabs were moved to 7nm and 6nm. Let’s call it the yield learning two-step where TSMC takes smaller process steps each year versus the much larger traditional semiconductor process steps.  For example, TSMC started EUV with a mature 7nm node then went full EUV at 5nm. Intel on the other hand is expected to go from zero EUV at 10nm to full EUV at 7nm.

Notable C. C. Wei quotes from the Q3 2020 Earnings Call:
“For TSMC, our technology leadership position enabled us to capture the industry megatrend of 5G and HPC. We expect to outperform the foundry revenue growth and grow by about 30% in 2020 in U.S. dollar terms.”

“This is pretty hard for me to answer, because I cannot release all the information I got from my customer. But let me say that, on the average, the 5G phone have about 30% to 40% more silicon content as compared with 4G.”

“We are complying full year with the regulations and so and we also notice that there is report saying that the TSMC got the (Huawei)  license. We are not going to comment on this unfounded speculation. And we also don’t want to comment on our status right now. For the 4Q shipment to Huawei, the ban, the regulation already say that after September 17th, zero.”

“Certainly TSMC is working with all the customers and view them as our partners. And so we don’t using this opportunity to raise our 8″ wafer price.”

“We are engaging with more customer at N3 as compared with the N5 and N7 at the similar stage. So there’s a lot of customers are working with us. And now, which one in the second half of 2022, which one would be the first product? Actually in smartphone and HPC applications, both.”

Bottom Line: TSMC and the rest of the semiconductor ecosystem seems to be somewhat COVID resistant. The new “work and learn from home” life style is accelerating the digital transformation and that means more semiconductors now and in the future.

About TSMC
TSMC pioneered the pure-play foundry business model when it was founded in 1987, and has been the world’s largest dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.

TSMC deployed 272 distinct process technologies, and manufactured 10,761 products for 499 customers in 2019 by providing broadest range of advanced, specialty and advanced packaging technology services. TSMC is the first foundry to provide 5-nanometer production capabilities, the most advanced semiconductor process technology available in the world. The Company is headquartered in Hsinchu, Taiwan. For more information please visit https://www.tsmc.com.

 

Posted on

ASML is Strong Because TSMC is Hot!

ASML is Strong Because TSMC is Hot!
by Robert Maire on 10-15-2020 at 10:00 am
Categories: Semiconductor Advisors, Semiconductor Services, TSMC
4 Comments

TSMC ASML EUV 2020
  • ASML has strong quarter lead by great Taiwan and EUV
  • EUV “crossed over” DUV as revenue leader- signaling new era
  • Taiwan doubles, China grows, Korea weaker, US further behind

ASML hits great numbers
ASML reported revenues of Euro 4B, with income of Euro 2.54EPS, both beating estimates handily. Ten EUV systems were shipped but 14 were recognized. Outlook is for revenues between Euro 3.6B-3.8B, which suggests upside to Euro 4B or better.

Shifting Numbers
There were significant shifts quarter over quarter. EUV went from 7 systems to 14 systems in Q3. Taiwan went from 21% of business to 47% with China going from 23% to 21% of business but increasing in absolute revenues. Korea slumped from 38% to 28% as EUV (which is not memory driven) dominated. The US (read that as Intel) fell off sharply fro.m 17% to 5%.

Intel “crushed” by TSMC in EUV spend- a very bad leading indicator
In the quarter Taiwan (primarily TSMC) was 47% of ASML’s business while the US (primarily Intel) was a paltry 5%. This means that TSMC is spending more or less ten times what Intel is spending on EUV.

In case there was any question as to who is winning Moore’s law by a tidal wave of investments. Intel investors should be scared…very scared. Intel is clearly voting with their feet and matching their words about outsourcing their future to TSMC, who is running away in the Moore’s law race. China spending four times what the US is spending (though none of it on EUV per the embargo) shows that China is deeply building out a strong semiconductor infrastructure and also clearly outspending the US.

Logic dominates at 79% versus memory of 21%
Logic at 79% is one of the highest percentages of revenues we have ever seen and is indicative of memory spending being subdued and perhaps weaker. The fact that this is so weighted to TSMC suggests that they are expecting a lot of business and also expect to put their foot on the EUV accelerator and leave both Intel and Samsung in their EUV dust. Memory obviously does not currently use EUV so the EUV domination of the current quarter will also outweigh memory DUV spend as ArF sales were down sharply.

Some “pushouts” and timing issues in the future?
A while ago we had talked about TSMC slowing spending and the pushouts and timing issues discussed on ASML’s call are likely related to what we heard as we may see some digestion in 2021 after its gigantic spending binge in 2020 (not unlike Samsung’s spending binge of a couple of years ago…).

This talk of pushouts and timing may spook investors but fits the pattern of our suggestion that the COVID led technology, work from home, spending spree will slow as the economic impact of COVID finally trickles down to the semiconductor industry.

Expect a lumpier business going forward
Given the dominance of EUV with systems north of $100M, a few systems more or less can make the quarters lumpier. Customer timing, pushouts and node changes will all add to lumpiness. The reality is that the end game of EUV and High NA remains the same and remains very good. The road to EUV itself was obviously very lumpy with fits and starts so investors should understand this. We would try to take a longer term view, though that may be difficult, and look at longer term trends.

Not much talk about “High NA”
We think that now that EUV is commonplace, the next upside wave will be High NA which will likely be easier (on a relative basis) as compared to the original EUV roll out. We think the potential technology benefits as well as financial benefits may make High NA more attractive than the EUV model. But High NA is still a few years away…..

Crossover from DUV to EUV – passing of the baton
ASML has now officially crossed over from being a DUV dominated company to an EUV dominated company. This brings a different set of challenges but a welcome set.

The key here is that they are the only EUV game in town so it cements their market share at virtually 100% versus having to compete (somewhat) at DUV. This makes the quite unique and valuable as compared to other semiconductor equipment companies who still slug it out in hand to hand battles. ASML is now “above the fray”

The Stocks
We don’t expect much movement on ASML’s stock price as it was already priced for the perfection we got. The talk of pushouts and timing may dampen sentiment and weigh on the stock and offset the positives. We do think it was prudent for management to keep expectations under control. At just over $400 per share ASML is not cheap nor expensive but appropriate given circumstances.

Collateral Stock Impact
In general we think that ASML’s strong performance first out in the quarter bodes well for the semiconductor equipment industry. Our main concern is that the stocks remain ahead of reality. The weak memory showing could be interpreted as bad for memory centric players, most notably Lam (though we have heard they are doing just fine) EUV spend clearly helps KLA and to a slightly lesser extent Applied.

Robert Maire

Also Read:

LRCX weak miss results and guide Supply chain worse than expected and longer to fix

Chip Enabler and Bottleneck ASML

DUV, EUV now PUV Next gen Litho and Materials Shortages worsen supply chain

Posted on

Three Things You Have Wrong About Intel!

Three Things You Have Wrong About Intel!
by Daniel Nenni on 10-09-2020 at 10:00 am
Categories: Foundries, Intel Foundry, TSMC
17 Comments

Three Things You Have Wrong About Intel

First let me tell you that I have nothing but respect for Intel. I grew up with them in Silicon Valley and have experienced firsthand their brilliance and the many contributions they have made to the semiconductor industry. In fact, I can easily say the semiconductor ecosystem would not be what it is today without Intel.

But no company is perfect and there have been many bumps and bruises along their 50+ year journey. The following is just my Intel opinion of course but I will put my semiconductor experience against anyone else in the mainstream media without hesitation.

1. Intel will go fabless

It all started with a story leaked a while back that Intel signed a big wafer deal with TSMC. Next Intel CEO Bob Swan said on a conference call that Intel was in fact looking at outsourcing and the media’s imagination went crazy after that.

Intel insight: CEO on U.S. manufacturing’s role in driving the digital revolution

To be clear, Intel has been a happy TSMC wafer customer for many years so that was not really news. Most, if not all, of it was the result of Intel acquisitions but the point is there has been a trusted Intel/TSMC relationship in place for a long time.

Intel is a semiconductor legend and manufacturing is in their DNA. Whoever says Intel will become fabless (like AMD did) clearly does not work inside the semiconductor industry. It is NOT going to happen.

Here is my professional Intel CEO assessment but first it is important to understand the first 30 years of Intel leadership. Intel was led by some of the top technical CEOs the semiconductor industry will ever see:

Robert N. Noyce
Intel CEO, 1968-1975, Co-founder of Fairchild Semiconductor
Education: Ph.D in physics, Massachusetts Institute of Technology

Gordon E. Moore
Intel CEO, 1975-1987, Co-founder of Fairchild Semiconductor
Education: Ph.D in chemistry and physics, California Institute of Technology

Andrew S. Grove
Intel CEO, 1987-1998, previously worked at Fairchild Semiconductor
Education: Ph.D. in chemical engineering, University of California-Berkeley

Craig R. Barrett
Intel CEO, 1998-2005, Joined Intel in 1974, chairman from 2005 until 2009.
Education: Ph.D. in materials science, Stanford University

The first 30 years of Intel can best be described by Andy Grove’s famous quote “Only the Paranoid Survive” which resulted in Intel being the most dominant semiconductor company in the world. Unfortunately, the next two Intel CEOs were NOT paranoid technical leaders which brought Intel to where it is today, NOT the most dominant semiconductor company in the world.

The current CEO is not a technical leader but he is a financial one and he did not grow up Intel. There is no Intel born swagger in Bob Swan. This is Bob’s big adventure to make his CEO bones in the business world and he will do whatever it takes to be successful as defined by Wall Street, not Moore’s Law. The one thing Bob Swan will NOT do however is erase the Intel manufacturing legacy and go fabless. Nobody wants that on their semiconductor CEO resume.

Intel Fab 42 in AZ now ready to pump out leading edge products

However, I do believe Bob will outsource Intel designed products to TSMC but only for the price and power competitive markets.

Partnering with TSMC will put Intel on a level manufacturing playing field with competitors and Intel will have much higher volumes so margins will be an advantage. Intel can then better focus their internal manufacturing efforts on HPC chips for the cloud which is where the majority of profits will come from over the next 10 years.

2. Intel will take TSMC wafers from AMD

You should also know that the chances of Intel buying up ALL of the TSMC wafers at a given node so AMD can’t have any is ZERO. Yet another dumb thing non semiconductor professionals are saying. Wafer agreements are put in place well in advance of the design start much less manufacturing. TSMC builds fabs based on wafer agreements so there are no capacity surprises, just ask Apple.

To be clear, it takes Intel and AMD longer to design a chip that it does for TSMC to build a fab, do the math.

3. AMD is beating Intel

That is a matter of debate of course. The company financials state otherwise but remember Intel has not had to look in their competitive rearview mirror at AMD since the AM386 more than 30 years ago. Clearly that is no longer the case, I can assure you AMD is in Intel’s competitive cross hairs moving forward. Thus the expanded outsourcing to TSMC, that is a clear shot at AMD. AMD acquiring Xilinx is a clear shot at Intel and Nvidia acquiring Mellanox and Arm is a clear shot at both AMD and Intel.

Bottom line: Competition is the life blood of the semiconductor industry so this is all great news for the ecosystem and the rest of the world, absolutely.

Thus far Bob Swan seems to have the right amount of paranoia to pivot Intel back into a dominant position so two thumbs up for Bob.

On a side note, in 2013 I strongly suggested privately and publicly that Intel should acquire Nvidia and make Jensen Haung Intel CEO number six. That would have been one hell of a ride! Instead Intel hired Brian M. Krzanich which is probably the biggest Semiconductor CEO dumpster fire on record.

Posted on

Will the U.S. and China go to War for TSMC?

Will the U.S. and China go to War for TSMC?
by Daniel Nenni on 10-05-2020 at 4:00 am
Categories: China, Foundries, TSMC
31 Comments

Will the U.S. and China go to War over TSMC

The semiconductor industry has never been more exciting than it is today and that is a mouthful given what we have accomplished over the last 50 years. From mainframe computers to a supercomputer in our pockets or on our wrists. Even if you don’t believe in miracles, semiconductor technology comes really close, absolutely.

U.S. tightens exports to China’s chipmaker SMIC, citing risk of military use REUTERS

When I started my career 36 years ago you would be hard pressed to find a person who had heard of a semiconductor much less knew what one really was. Today, it is still hard to find people who really know semiconductor design and manufacture (especially in the media) even though you can read about it every day, especially now that semiconductors could lead to the next world war.

Before you write me off as another click-baiting-chicken-little think about how important semiconductors are to modern life. Not just important, semiconductors are critical to modern life. Not just critical, semiconductors could mean the difference between life and death.

Disagree? Imagine our world without electronic devices. Imagine a business or hospital without digital equipment. Imagine a military without high tech gear. Are you getting the picture? Life or death.

Now understand that semiconductors are where modern electronics begin and end for that matter. Also understand that the semiconductor chip may have been invented in the United States but today it is a worldwide supply chain.

To be clear, no one country can succeed in semiconductor design and manufacture without others. Having grown up in Silicon Valley and spending the majority of my semiconductor professional life traveling the world I know this firsthand, front row seat, I lived it.

Being from a military family and a military history enthusiast I also know a little bit about war. My grandfather served in WWI as an Army medic and lived to tell about. In fact, he lived 102 years under my care so I heard all about it. My other Grandfather was at Pearl Harbor, my father served in Korea, and my Uncle in Vietnam. War is hell.

One of the strategic things to do when waging a war is to cut off their supply lines, right? Food, water, fuel, raw materials, etc… You can now add semiconductors to that supply list.

So why is the United States today cutting off the semiconductor supply line to China? It’s an act of war and if there is an actual war over semiconductors, where will it be fought?

Taiwan of course. Taiwan is the semiconductor manufacturing hub of the world. Taiwan is also the Republic of China, which is what my passport says, and even without semiconductors China wants political control over Taiwan. Something like what is happening in Hong Kong only with a full-on war declared.

Why is Taiwan so important to the semiconductor supply chain? Because Taiwan is the home of TSMC (Taiwan Semiconductor Corporation), the worldwide champion of semiconductor manufacturing. My first book “Fabless: The Transformation of the Semiconductor Industry” goes into more detail on how TSMC came about but the bottom line is; It’s all about the ecosystem (supply chain). Hundreds of companies around the world brought us to where we are today and nothing short of a war can stop the semiconductor ecosystem from succeeding.

Could it even be possible? China at war with the US through Taiwan? Ten years ago from the Lobby of Hotel Royal in Hsinchu I would have said absolutely not. Today, sheltering in Silicon Valley, given the current political instability and oncoming economic challenges, given the eye-for-an-eye +1 behavior of the US and China leadership, I say war is probable. Unless of course the world recognizes semiconductors as a matter of life or death and gets civilized around it. Just my semiconductor professional opinion of course.

Posted on

5G, Hyperscaling and the Resurgence of Consumer Silicon

5G, Hyperscaling and the Resurgence of Consumer Silicon
by Ramsay Allen on 10-04-2020 at 6:00 am
Categories: 5G, IP, Moortec, TSMC

TSMC 5G OIP 2020

At the recent TSMC OIP Ecosystem Forum and Technology virtual events, TSMC re-affirmed their previous prediction that 5G is going to be a multi-year silicon mega-trend with the biggest drivers being the ramp up of 5G handsets, supporting infrastructure and the continued growth of high performance computing (HPC).

We all want the luxury of live streaming, whether it be a concert or sports event, playing the latest games or watching HD movies on our phone, but what is it that actually allows 5G ASIC designers to deliver this enhanced level of user experience? Today’s Semiconductor advanced node technology really is the beating heart of 5G network technology.  Powering network base stations, cars, smartphones, and other connected devices, but 5G also plays an integral part of a much bigger technology phenomenon…Hyperscaling.

5G infrastructure is extremely power hungry and generally requires ~3 times the number of base stations compared to older technologies such as LTE, due to the higher frequencies involved. Moortec is already working with customers in the 5G space to help address some of these infrastructure power issues.

5G Silicon Challenges

5G enabled devices such as handsets, tablets and wearables have certainly helped revitalize the consumer electronics space as they have moved from typically planar nodes down to FinFET process technologies like 5nm.

This step change does however present designers with specific challenges, one of the biggest being increased thermal activity associated with the data intensive workloads associated with the system​. Battery life can also be an issue when running 5G and associated applications like video, and gaming etc. If the thermal conditions are not carefully monitored and controlled, handsets may either switch to a lower power 4G mode or even turn off altogether. As a user why do I care? Well, apart from the handset becoming noticeably warmer to the touch, your video download will take longer or freeze and your phone will need recharging more frequently as the battery will drain faster.

A 5G small cell can be operational for over a decade in potentially hostile environments, without any forced air cooling and as such it is particularly important to be able monitor them remotely in the field.

Moore’s Law

In the last instalment of the Moortec ‘Talking Sense’ blog my colleague Tim Penhale-Jones talked about the impact that Moore’s law and Dennard Scaling have had on the advanced node semiconductor sector. For some time, we have been cramming ever increasing amounts of processing power into each 1mm2 of silicon and this has enabled the 5G technology that we see emerging today. However, the pressure continues to Miniaturize (device size), Maximise (power & performance) and Optimize (reliability & battery life) and in order to continue to do this successfully it is critically important to understand the dynamic conditions within the device itself.

Benefits of In-Chip Monitoring for 5G Devices

By implementing highly configurable, real time embedded sensing fabrics, chip designers can address some of the challenges associated with overheating, reduced data throughput and diminished battery life. This enhances the overall user experience in consumer products like 5G handsets and increases the performance optimization and reliability of infrastructure devices in the field.

To find out how Moortec’s in-chip monitoring technologies and sensing fabrics could benefit your next advanced node 5G project contact us today.

In case you missed any of Moortec’s previous “Talking Sense” blogs, you can catch up HERE.