TSMC – Page 17 – SemiWiki

January 13, 2020July 6, 2020

The Tech Week that was January 6-10 2020

The Tech Week that was January 6-10 2020
by Mark Dyson on 01-13-2020 at 6:00 am
Categories: China, Foundries, TSMC

Happy New Year to everyone.. lets hope 2020 is a great year.. The indicators are all pointing in the right direction but it will not take much to derail it if external factors change. Here is my weekly summary of all the important news from the semiconductor industry around the world.

2020 is starting very differently from 2019 with much optimism around. This article in Semiconductor Engineering surveys CEO’s across the industry to get their views on 2020. 5G, AI and big data are all factors that should be big this year and help drive the recovery.

CES was held last week with many new consumer ideas on display. Smart homes was certainly one of the hot topics with smart speakers for the shower, smart frying pans that weight your food and smart cooker hobs that you can control by voice, smart shelves for monitoring your groceries amongst some of the items on display. One item that would certainly be useful in Singapore was a device that instantly cools the object placed in it, like a reverse microwave, it can cool a can of beer in 2minutes. 8K TV’s were on display as were foldable computers, and of course there were lots of robots and AI applications. Here are some articles about the technology on display in the show. An overview from the BBC, the standout gadgets by the Guardian, the key takeaways by the Verge.

The Taiwan foundries ended the year on a high. TSMC hit another record high for the quarter, the second successive quarter it achieved this. Q4 revenue was US$10.5billion, up 8% sequentially. December revenues were down 4% sequentially at US$3.44billion but was up 15% on a year ago.

UMC saw revenues surge in December up 17.4% from a year ago, reporting revenues of US$445million. Q4 revenues were also up 17.4% on a year ago, mainly due to the additional revenues from the taking full control of Mie Fujitsu foundry in Japan.

Specialty foundry Vanguard (VIS) didn’t fair quite so well in Q4, reporting Q4 revenues were down 2.2% on year ago at US$87million.

For the back end assembly test provider ASE reported Q4 revenue up 8.9% YoY at US$2.27billion and up 4.1% sequentially for the ATM group. December revenue was up 2.5% on November with revenue of US$771million, this was up 16% on a year ago.

Market research company IC Insights reported that the pure play foundry market decreased 2% globally in 2019 compared to a year ago. China was the only region to see an increase in pure play foundry market last year growing 6%. Taiwan foundry TSMC reported that approx. 25% of it’s customers were in China.

One of the side effects of trade wars is that it prompts countries to become more self sufficient. As a result of the trade war between South Korea and Japan, South Korea has announced Dupont will invest $28million in South Korea to develop advanced photoresists and other materials by 2021 to allow South Korea to be less dependent on Japan supplies.

Similarly in China, China is pushing to decouple it’s technology from the US as a result of the US-China trade war which has lead to a boom for some Chinese tech companies.

It appears that the US put a lot of pressure on the Netherlands to prevent ASML from delivering a EUV lithography tool to China and to cancel the sale.

Despite the trade war and the ban on Huawei, Huawei still managed to grow it’s revenue in 2019 by 18% to US$121.7billion, though this was lower than originally predicted due to the trade war preventing the company access to source parts. Huawei said that 2020 will be a difficult year and it will not be able to grow as fast and only grow by 3.9%.

It is reported that production was impacted at its Samsung Electronics Hwaseong plant due to a minute long power blackout. It is speculated that the incident caused million of dollars in losses.

January 3, 2020August 31, 2020

Semiconductor Review 2019 into 2020!

Semiconductor Review 2019 into 2020!
by Daniel Nenni on 01-03-2020 at 6:00 am
Categories: China, Foundries, TSMC

Semiconductors continue to surge and lead technology sectors all over the world. TSMC has always been my economic bellwether and 2019 was another great year as the TSM share price almost doubled. But it looks like the best is yet to come with TSMC significantly increasing CAPEX to cover 7nm and 5nm demand.

TSMC CEO C.C. Wei increased 2019 CAPEX from $10.5B in 2018 to more than $14B in 2019 with a big Q4 spend. Remember, TSMC builds capacity based on customer orders and not a dart board forecasting. With TSMC winning both the 7nm and 5nm popular vote, 2020 should be another blockbuster CAPEX year to backfill demand.

There are two VERY disruptive semiconductor trends to watch in the next year or three and that is the large systems companies taking control of their silicon (including Google, Facebook, Amazon, Microsoft, etc…) and China also taking control of their silicon.

Apple started it and now all systems companies in competitive markets will follow. It will be interesting to see who the big players are at CES 2020 next week and more importantly how many of them are making their own chips. My bet would be the majority of them including the automakers. It’s not really a fair bet since SemiWiki.com is the leading semiconductor design enablement portal with more than 3.25 million unique views and we get to see who reads what, when, and where they are from.

Why are systems companies dominating semiconductor design? Because they can use prototyping and emulation to get a jump on verification and software development and really tune the silicon to the system. Systems companies are also VERY competitive and can write some VERY big checks and they will not miss tape-outs or product ship dates. This is so un-fabless-like it isn’t even funny. It really is a new semiconductor world order.

Speaking of a new world order, China is also disrupting the semiconductor industry with billions of dollars invested in the “Made in China 2025” semiconductor supply chain initiative.

Think about it, China consumes more than 50% of semiconductor production worldwide and they only produce about 20% of said chips. My guess is 2020 and 2021 will see unprecedented China chip manufacturing growth due to increased memory (DRAM and NAND) manufacturing capacity coming online. Add in the political turmoil motivator and memory hogging mobile, 5G and AI, the Made in China 2025 initiative will get a major boost, my opinion.

I will be in China again this month and am excited to see what’s new. You can Google around all you want but there is nothing like being there.

2019 was also a big year for SemiWiki.com. We unleashed SemiWiki 2.0 in June with many new cloud-based features and more to come. Traffic and member registration is again growing double digits and we are already working on SemiWiki 3.0.

I would truly like to thank all of our bloggers, partners, readers, and registered members for your continued support. SemiWiki has been an exciting 10 year adventure and I’m looking forward to working with you all in the coming years. After spending my entire 35+ year career in semiconductors I can say that without a doubt the best is yet to come, absolutely!

January 1, 2020January 8, 2021

ANSYS, TSMC Document Thermal Reliability Guidelines

ANSYS, TSMC Document Thermal Reliability Guidelines
by Bernard Murphy on 01-01-2020 at 6:00 am
Categories: 5G, Ansys, Inc., EDA, FinFET, Foundries, TSMC

Advanced IC technologies, 5nm and 7nm FinFET design and stacked packaging, are enabling massive levels of integration of super-fast circuits. These in turn enable much of the exciting new technology we hear so much about: mobile gaming and ultra-high definition mobile video through enhanced mobile broadband in 5G, which requires support for millimeter wave frequencies; high-speed networking in hyperscalar datacenters through 100G connectivity; blazing fast AI accelerators in those same datacenters; and fusion of multiple sensor sources to build environment-aware intelligence for automotive safety and autonomy, building security, autonomous drones and many more capabilities.

With new technologies we always find new challenges. ANSYS and others have been hearing from chip and system builders supporting these domains that they are seeing increasing post-silicon failures in the devices they are building. These devices are nominally perfectly fine, pass standard testing, but fail in system operation primarily related to voltage, timing and process variations. Tianhao Zhang (Dir. Foundry Relations at ANSYS) says that between what they are hearing from customers and industry reviews, 75% of these product failures can be attributed to thermal or vibration effects.

Thermal also increases cost through need for more advanced cooling, it reduces performance through increased resistance in the interconnect and degraded transistor performance and it increases noise leading to random failures. It also decreases reliability, on chip through electromigration and device aging, and in the package and system through mechanical stress during to warping.

This is not a problem that can be dealt with later. One chip design VP has said that self-heating (related to FinFETs) and thermal analysis are now absolute requirements for automotive and high-performance computing applications. Another noted that compared to planar designs they are now seeing temperature increases in metal of 10 to 20 degrees, and that is making design for reliability much more challenging.

TSMC has been hearing all the same issues and has been increasing the number of checks they require, particularly thermal checks, to offset these types of problem. TSMC has worked closely with ANSYS to prove and document a thermal solution they jointly support. This includes an ANSYS reference flow for transistor, chip and package/3D-IC levels, from 20nm down to 5nm. These can be downloaded from the TSMC portal.

They are also working together on solution guides for specific application flows. For example, ANSYS now provides solution guides for automotive development on 16nm and 7nm. These cover electromigration, thermal and ESD topics. In the thermal analysis section, the document details multiple areas including the flow, and also provides test cases and case studies.

The ANSYS analysis is not based on a simple averaging of thermal effects. They analyze all the way down to the physical implementation of transistors and interconnect systems under representative activity scenarios, to estimate local heating, interconnect heating and heat dissipation. They do this using analytics from RedHawk, together with finite-element analysis applied at the die, stacked die, package and board level. And they’re computing temperature profile by looking at (thermal) conduction, radiation and convection flows, the last of these though detailed fluidics analysis. This is a true bottoms-up multi-physics solution. You can learn more in THIS WEBINAR, presented by Tianhao and Karthik Srinivasan (Sr Prod Mgr at ANSYS).

December 30, 2019September 1, 2024

TSMC, Huawei, the US Government, and China

TSMC, Huawei, the US Government, and China
by Daniel Nenni on 12-30-2019 at 6:00 am
Categories: China, Foundries, Samsung Foundry, TSMC
2 Comments

The media is trying to disparage the semiconductor industry again. It’s hard to not take this type of desperate journalism personal. Semiconductor people are the smartest and hardest working people in the world and we deserve better, absolutely.

Morris and Sophie Chang TSMC

TSMC founder sees trade dispute as ‘reality show with no script’ July 2018

The latest media scam is that the US Government is pressuring TSMC about stopping wafer shipments to Huawei (HiSilicon). The Financial Times started it with “US urges Taiwan to curb chip exports to China” and the cut/paste media sites jumped all over it and “made it their own”.

TSMC responded with:

“We did not have any discussion with either the Taiwan or the U.S. governments regarding shipping wafers to HiSilicon, nor have we received any instruction from either government not to make the shipments,” TSMC spokesperson Elizabeth Sun told Caixin in an email, adding that it will continue shipments while complying with trade regulations.

Remember, TSMC has two fabs in China and plenty of room for expansion. The US accounts for 61% of TSMC’s revenue and China is a growing 17%. Taiwan is 8%, Japan 6% and others are 1%. The question is: What would happen if TSMC cut wafer shipments to the US or China? Answer: The end of modern life as we now know it.

Another ignorant quote:

“Last month, a U.S. official informed Taiwanese diplomats that the semiconductors produced by TSMC and then procured by Huawei, were ending up in Chinese missile guidance systems aimed at Taiwan, as per the reporting by Financial Times.”

I can assure you TSMC knows more about what their customers are doing than politicians in any country including Taiwan. There are very few secrets inside the fabless semiconductor ecosystem and TSMC knows more than most. And does it really matter who made what, when, and where in the case of war? It doesn’t matter because there is nothing you can do about it. That ship sailed a long time ago.

Bottom line: TSMC is the new Switzerland and has the full support of the US, Taiwan, and China Governments.

Another interesting headline:

“Samsung is pouring $116 billion towards beating TSMC in the race to 5nm and beyond”

First and foremost, TSMC has already won the race to 5nm and EUV if the finish line is high volume manufacturing versus press releases or “leaked” road maps.

In order for Apple to ship millions of iProducts in Q4 2020 the 5nm EUV process must be frozen by the end of 2019 starting production in Q1 2020. In fact, TSMC recently outlined their 5nm process at IEDM.

I remember when SMIC launched in 2000 and suggested that they would compete with TSMC. It was believable to me because the China Government was strongly behind them and the China consumer market was theirs for the taking. Unfortunately, competing with TSMC proved too hard for SMIC who then resorted to stealing trade secrets. The resulting litigation cost SMIC hundreds of millions of dollars and 10% of their stock.

To say that SMIC is a trailing edge foundry is quite generous. SMIC has just now released a 14nm process four years after TSMC who is now at 5nm with full EUV. SMIC doesn’t even have an EUV machine yet and they may not get one if the current political turmoil is not properly addressed.

According to reports, the SMIC 14nm was co-developed with Qualcomm who also worked with TSMC and Samsung on 14/16nm processes. I’m sure the TSMC and Samsung legal staff already have SMIC 14nm die under review.

GlobalFoundries also had their sites set on competing with TSMC but that never really happened, not even close.

Samsung officially became a pure-play foundry in 2017 when they reorganized all of their logic fabs under Samsung Foundry. Samsung Electronics is Samsung Foundry’s biggest customer of course but they do have a long history of external foundry business. Apple was the big start with the introduction of the iProducts and other big fabless companies (Qualcomm) have followed.

Samsung certainly is a leader in connectivity and IoT now that all Samsung appliances, TVs, and other electronic gadgets have WiFi so they can talk to you throughout the day. You should see the Samsung booth at CES. It’s more of a connected city than a trade show booth but I digress.

Bottom line: While Samsung’s “pouring $116 billion towards beating TSMC” is impressive you have to understand that the TSMC ecosystem of partners and customers have poured trillions of dollars into TSMC staying ahead of all foundry comers, right?

December 16, 2019August 22, 2024

IEDM 2019 – TSMC 5nm Process

IEDM 2019 – TSMC 5nm Process
by Scotten Jones on 12-16-2019 at 10:00 am
Categories: FinFET, Foundries, GlobalFoundries, Intel Foundry, Samsung Foundry, TSMC
10 Comments

IEDM is in my opinion the premiere conference for information on state-of-the-art semiconductor processes. In “My Top Three Reasons to Attend IEDM 2019” article I singled out the TSMC 5nm paper as a key reason to attend.

IEDM is one of the best organized conferences I attend and as soon as you pick up your badge you are handed a memory stick with all the conference papers (unlike some other conferences where there are no proceedings). It is very useful to get the papers before seeing them, I typically review a paper, see it presented, and then review it again. I quickly previewed the TSMC paper in advance of the presentation and I have to say I was very disappointed with the lack of real data in the paper, there were no pitches and most of the results graphs were in normalized units. At the 2017 IEDM conference Intel and GLOBALFOUNDRIES (GF) presented their 10nm (7nm foundry equivalent) and 7nm processes respectively and both companies provided critical pitches and electrical results in real units. You can see my previous write up on these papers here.

I would like to take this opportunity to call on TSMC to provide more transparency with respect to their processes.

At the press lunch on Monday many of the IEDM session chairs were available and I asked them about this paper and whether they ever push back on companies to provide more data or reject a paper for lacking enough detail. The answer I got back was yes and in fact they turned down a platform paper from another leading logic company this year for lack of data and said they debated whether to let the TSMC paper in. It is a difficult position for the organizers, this is the kind of headline paper that attracts attendees but at the same time the conference must maintain a standard of quality.

In the balance of this article I will discuss what TSMC disclosed and then try to fill in some of the details they didn’t disclose based on my own investigations. I have read the paper, seen the paper presented, and asked the presenter a question at the end of the presentation and discussed this process with a wide range of industry experts.

TSMC’s disclosures
The key bullet points from the TSMC paper and presentation are:

Industry leading 5nm process.
Full fledged EUV, >10 EUV layers replacing >3 immersion layers each resulting in a reduction in mask count improving cycle time and yield. The paper says >4 immersion layers for each EUV layer but in the presentation the presenter said >3.
High mobility channel FETs.
021µm2 high density SRAM.
~1.84x logic density improvement, ~1.35x SRAM density improvement and ~1.3x analog density improvement.
Gate contact over diffusion, unique diffusion termination, EUV based gate patterning for logic and SRAM.
~15% speed gain or 30% power reduction.
Low resistance and capacitance interconnect with enhanced barrier lines and etch stop layer (ESL) with copper reflow gap fill. The Back-End-Of-Line (BEOL) also features a high resistance resistor for analog use and super high-density Metal-Insulator-Metal (MIM) capacitors
5 and 1.2 volt I/O transistors.
True multi-threshold voltage process with 7 threshold voltages over a >250mv range supported and an extreme low Vt transistor 25% faster than the previous generation. Presumably only around 4Vts are available at a time.
Passed qualification.
High yielding test chip with 256Mb SRAM and CPU/GPU/SOC blocks and D₀ ahead of plan with a faster yield ramp than any previous process. 512Mb SRAM has ~80% average yield and >90% peak yield.
In risk production now with 1^st half 2020 planned high volume production.

Density and pitches
At 7nm Samsung and TSMC have similar process densities. Moving from 7nm to 5nm Samsung has disclosed a 1.33x density improvement and TSMC has disclosed a ~1.84x density improvement. Clearly TSMC will have a far denser process than Samsung and with Intel’s 7nm (5nm foundry equivalent process) not due until 2021, TSMC will have the process density lead in 2020.

In terms of specifics other than an SRAM cell size of 0.021µm2 TSMC didn’t provide any. SRAM density is certainly important for SOC designs where SRAM can often make up over half the device area.

Logic designs are created with standard cells. The height of a standard cell is the Metal 2 Pitch (M2P) multiplied by the track height (TH) and the width is defined by the Contacted Poly Pitch (CPP), cell type and whether the process supports single or double diffusion break. For the TSMC 7FF process M2P is 40nm and the TH is 6. The CPP is specified as 54nm although 57nm is seen in standard cells, however since TSMC stated their density improvement we will assume 54nm as a starting point and the process supports a double diffusion break (DDB). Running these dimensions through the Intel density metric we have discussed before yields 101.85 million transistor/mm².

I have heard that TSMC is going to use a very aggressive 28nm M2P at 5nm and I also believe they will stay with a 6-track cell. A 5-track cell requires Buried Power Rails (BPR) and TSMC did not disclose that as part of the process, I also believe it is too early to see BPR in a process. I also expect this process to support Single Diffusion Break (SDB), SDB was added with the 7FFP version of TSMC’s 7nm process and I believe they will maintain that. The net result is for a 1.84 density improvement CPP is between 49 and 50nm. If I assume 50nm I get 185.46 MTx/mm2 a 1.82x improvement in density.

Figure 1 presents a 7FF versus 5FF process comparison.

Figure 1. TSMC 5FF Process Density.

EUV usage
As I stated previously, the paper mentions a single EUV layer replaces >4 immersion layers although the presentation revised this to >3 immersion layers. The paper and presentation both report 5nm using >10 EUV layers and that would imply >30 immersion layers will be replaced. This is presumably versus the number of immersion layers required if 5FF were done with multi patterning instead of with EUV.

In the article a graph of mask layers is presented with normalized units where 16FFC is 1.00, 10FF ~1.30, 7FF ~1.44 and 5FF ~1.30. I believe TSMC’s 7FF process is 78 masks and the 5FF is 70 masks. When I use my mask estimates for 16FFC, 10FF, 7FF and 5FF I reproduce the graph from the paper nicely.

I also believe TSMC’s 7FFP process has ~5 EUV masks and 5FF will have ~15 EUV masks.

Another interesting EUV comment, I am hearing Samsung has a very high dose for their EUV process for critical layers and I have heard TSMC’s EUV dose is much lower with TSMC a >2x throughput advantage over Samsung> This is also consistent with reports that Samsung is having trouble getting enough wafers through their EUV tools. At another conference I saw an IBM presentation where they discussed developing the 5nm process with Samsung. They said that they turned up the EUV dose until they got good yield and transferred the process to Samsung with the idea that Samsung would then work on reducing the dose. It sounds like the process may have been rushed into production before reducing the EUV dose.

High mobility channels
I have been expecting for some time that Silicon Germanium (SiGe) High Mobility Channels (HMC) will be introduced at 5nm for pFETs.

When I got the TSMC paper and read through it they talk about HMCs plural and even have a figure that says HMC and show both nFET and pFET results, they further show HBC on silicon with no interface buffer layers. The only answer that fits this in my view would be if TSMC had implemented Germanium channels for both nFET and pFET devices, but I thought that was an advance that wasn’t ready yet. If that were the case this would be similar to Intel introducing High K Metal Gates (HKMG) at 45nm or FinFETs at 22nm.

After the TSMC talk I asked the presenter whether the nFET and pFET devices were both HHC or just the nFET or just the pFET. The presenter responded that only one of the device types had HMC although he wouldn’t say which one. I believe it is almost certain that the pFET is a SiGe channel as expected.

Conclusion
In conclusion TSMC has developed a high density 5nm process that will provide the industries highest process density in 2020 and establishes TSMC as the current leader in logic process technology.

December 9, 2019January 10, 2020

As 2019 comes to an end everyone is starting to look at what 2020 holds

As 2019 comes to an end everyone is starting to look at what 2020 holds
by Mark Dyson on 12-09-2019 at 10:00 am
Categories: China, Semiconductor Services, TSMC
3 Comments

At the moment there are many encouraging signs based on the latest data. Let’s hope this trend continues into 2002 and 2020 is the year of recovery of the semiconductor market. However much depends on how the US China trade war pans out. Last week Trump blew hot and cold saying everything from the negotiations were going very well to saying that he thought there may not be an agreement until after the US presidential election next year. The next round of additional US tariffs are due to go in place on December 15th, so hopefully there will be enough progress to delay the imposition of these.

According to IHS Markit, global semiconductor sales dropped 14.2% in the first 3 quarters of 2019 compared to 2018, but there are signs of recovery even in the memory segment which has dragged down the sector so far. Intel retained it’s number 1 position with 16.3% revenue growth in Q3. For the full year IHS Markit estimate sales will recover slightly and only drop 12.4% compared to 2018.

For 2020, they estimate that NAND flash will grow 19%. Strong growth in NAND flash and DRAM is forecast as momentum increases for 5G connectivity, artificial intelligence, deep learning, and virtual reality in mobile, data center and cloud-computer servers, automotive, and industrial markets in 2020.

SEMI reported that October global semiconductor sales rebounded in October with a 2.9% month on month increase with global sales of US$35.6billion, but this was still down 13.1% yoy.

Meanwhile the World Semiconductor Trade Statistics (WSTS) organization projects annual global sales will decrease 12.8 percent in 2019, before the market starts to recover with increases of 5.9 percent in 2020 and 6.3 percent in 2021.

SEMI also published it’s 3rd quarter global semiconductor equipment manufacturers billings data showing a 12% growth over Q2, but still down 6% compared to Q3 2018. Taiwan regained the worlds largest semiconductor market status by growing 21% from Q2, and up 34% from a year ago, buying $3.9billion of equipment. Taiwan was ranked third in semiconductor equipment purchases throughout 2018, behind South Korea and China before taking top slot in Q1, and 2nd in Q2 to China. TSMC capex spending accounted for $3.21billion of the total as it invested to support 7nm, 5nm and 3nm technologies.

In addition TSMC announced it plans to spend US$14~15billion on capital expenditure next year, more than half of this expenditure is going to be spent on expanding its 5nm technology to support 5G technology growth. TSMC see a much stronger than expected demand for 5nm & 7nm due to the rapid deployment of 5G around the world. TSMC also confirmed it is on schedule to start mass production of 3nm in 2022.

Taiwanese foundry UMC has announced that it has released 22nm technology for production.

Taiwan’s manufacturing index hit a 15 month high last month due to strong demand from the electronics sector driven by 5G applications. The PMI increased from 52.7 in October to 54.9 in November with the sub index of new business orders climbed from 52.7 to 61.

In South Korea the outook is not so rosy with export orders of semiconductors decreasing 31% to US$7.4billion in November, the 12th straight month of decline. However market analysts are hopefully of a recovery soon as the Chinese PMI rebounded to 51.8 in November.

Huawei CEO Ren Zhengfei has said it plans to shift it’s US based research centre to Canada. He also said he wants to build some new factory capacity in Europe to build 5G networking equipment.

According to Bloomberg, Chinese semiconductor companies are stockpiling US semiconductor chips in case the trade war worsens and US cuts off access to US technology. In past 3 years Chinese purchases of IC’s has risen strongly, and in the last 2 months imports have been the highest since the start of 2017.

Elsewhere in China Xiaomi and Oppo both announced that they will use Qualcomms latest 5G Snapdragon 865 chip for the flagship smartphones to be released in Q1 next year.

According to the EETimes, ChangXin Memory is emerging as Chinas leading DRAM manufacturer, and is currently running 20,000 wafers per month at its Fab in Hefei. It is currently using 19nm technology to produce LPDDR4, DDR4 8Gbit DRAM products. It has plans to double it’s production in Q2 2020.

In company news, AMS has announced it has succeeded in it’s 2nd bid for Osram having managed to acquire above the required 55% of shares for it’s €41/share bid for the company which values the company at €4.5billion.

Also STMicrolectronics has announced it has acquired the remaining 45% of Swedish silicon carbide wafer manufacturer Norstel AB. Norstel develops and manufactures 150mm silicon carbide (SiC) bare and epitaxial wafers.

December 9, 2019January 13, 2022

Bob Swan says Intel 7nm equals TSMC 5nm!

Bob Swan says Intel 7nm equals TSMC 5nm!
by Daniel Nenni on 12-09-2019 at 6:00 am
Categories: Foundries, Intel Foundry, TSMC
20 Comments

Bob Swan is really starting to grow on me. Admittedly, I am generally not a fan of CFOs taking CEO roles at semiconductor companies but thus far Bob is doing a great job. This comes from my outside-looking-in observations and from the people I know inside Intel, absolutely.

Bob did a fireside chat with Credit Suisse at their 23^rd annual technical conference which is now up on the Intel website HERE. It is 51 minutes and definitely worth a listen while sorting laundry or getting a mani pedi.

The media really latched onto Bob’s comments about destroying the Intel idea of keeping the 90% CPU market share and focusing on growing other market segments. Dozens of articles hit the internet by people who have no idea what they are talking about so don’t waste your time.

The most interesting comments to me were in relation to TSMC. According to Bob Swan Intel 7nm is equivalent to TSMC 5nm, which I agree with, I just do not remember an Intel CEO ever saying such a thing. He also said that Intel 5nm will be equivalent to TSMC’s 3nm to which I am not so sure. Making a FinFET to FinFET process equivalency statement is fine but from what I was told Intel will be using Nanosheets at 5nm.

Bob also talks about Intel’s transitions from 22nm to 14nm to 10nm in very simple terms. 22nm to 14nm had a 2.4x density target which as we now know was a very difficult transition. From 14nm to 10nm Intel targeted a 2.7x density target which led to even more manufacturing challenges. Intel 7nm with EUV will be back to a 2.0x scaling target.

Remember, Intel was on a two year process cadence until 14nm. Intel 22nm was launched in 2011, 14nm came 3 years later (2014), and 10nm 5 years after that. Intel 10nm was officially launched in 2019 and Intel 7nm is scheduled for late 2021 which I have no doubt they will hit given the above targets.

TSMC on the other hand delivered 16nm in 2015, 10nm in 2017, and 7nm in 2018. TSMC will deliver 5nm in 2020 and 3nm (also a FinFET based technology) is scheduled for 2022. You can expect 5nm+ to fill in the gap year just as 7nm+ did in 2019. Remember, TSMC is on the Apple iProducts schedule so they have to be in HVM early in the year versus late for Apple to deliver systems in Q4. Intel just has to ship chips.

Bottom line: TSMC is still about a year ahead of Intel on process technology and I do not see that changing anytime soon, my opinion.

I am at IEDM 2019 this week with SemiWiki bloggers Scott Jones and Don Draper (new blogger) so stay tuned. TSMC is giving a paper on 5nm and of course the chatter in the hallways has even more content.

TSMC to Unveil a Leading-Edge 5nm CMOS Technology Platform: TSMC researchers will describe a 5nm CMOS process optimized for both mobile and high-performance computing. It offers nearly twice the logic density (1.84x) and a 15% speed gain or 30% power reduction over the company’s 7nm process. It incorporates extensive use of EUV lithography to replace immersion lithography at key points in the manufacturing process. As a result, the total mask count is reduced vs. the 7nm technology. TSMC’s 5nm platform also features high channel mobility FinFETs and high-density SRAM cells. The SRAM can be optimized for low-power or high-performance applications, and the researchers say the high-density version (0.021µm2) is the highest-density SRAM ever reported. In a test circuit, a PAM4 transmitter (used in highspeed data communications) built with the 5nm CMOS process demonstrated speeds of 130 Gb/s with 0.96pJ/bit energy efficiency. The researchers say high-volume production is targeted for 1H20. (Paper #36.7, “5nm CMOS Production Technology Platform Featuring Full-Fledged EUV and HighMobility Channel FinFETs with Densest 0.021µm2 SRAM Cells for Mobile SoC and High-Performance Computing Applications,” G. Yeap et al., TSMC)

AMAT last to confirm foundry led recovery

AMAT last to confirm foundry led recovery
by Robert Maire on 11-18-2019 at 6:00 am
Categories: Foundries, Semiconductor Advisors, Semiconductor Services, TSMC
2 Comments

Good end to a weak fiscal year- and end to down cycle
As expected and well telegraphed by TSMC, LRCX, ASML & KLAC, AMAT put up a good quarter and guide as the last to report that the industry has turned the corner on the down cycle. While not a rip roaring recovery, its better to return to growth than continue a downward trend.

Results were at the high end of guidance coming in at EPS of $0.80 versus street of $0.76 and revenues of $3.75B versus $3.68B. More importantly, guidance for the January quarter is for $0.87 to $0.95 on revenues of $4.1B +- $150M.

No surprise here- All driven by TSMC
Its quite clear that the hockey stick like huge uptick in TSMC spending focused on the end of year is the primary reason for AMATs strong outlook. While Intel has been tepid at best and memory is still dead with display going nowhere, its TSMC that is carrying the entire load of the recovery. Their uptick is so strong it has been able to offset the weakness in other areas.

We would remind investors that Applied has one of the strongest relationships with TSMC of any equipment supplier, having TSMC been called :the house that Applied built”. It is somewhat funny that whereas in the past relationship TSMC needed Applied to be a force in the chip industry, now the tables are turned and Applied has TSMC to thank for the recovery.

Running on 5 of 8 cylinders
Applied repeated what we have been saying for many months now, that this up cycle will be driven by foundry/logic. Memory remains virtually dead and display treading water at best.

The question is when do those 3 cylinders- DRAM, NAND & Display start firing again? We certainly agree with Applied by saying its a question of when not if.

On the call the company was very careful, multiple times, not to comment on the shape or size of the recovery. The company also demurred on the question of a potential 2020 recovery of NAND and left out entirely the timing of a DRAM recovery.

Given that capacity has still been coming off line recently in memory it will be a fairly long time before memory spending starts up again. In our view, its unclear if NAND will recover before the end of 2020.

Who benefits most from a Foundry/Logic recovery?
Given that this up cycle is very much led by foundry/logic with memory stuck in neutral, we think its appropriate to revisit who has the best exposure to foundry/logic of the big 4 semi equipment makers.

We think its clear that KLAC is likely the highest exposure to foundry/logic and historically has been viewed as the anti-memory play. TSMC is spending a lot of money on process control keeping on their annual improvement cadence and KLA gets the lions share of that.

Applied is likely second in line to foundry/logic exposure with a long history of support of TSMC, but still very dependent upon memory for its business. Applied will see a mild recovery but really needs memory to kick back in.

ASML is likely third as it gets most of its EUV business from TSMC but still relies on DUV and memory as being volume buyers of scanners making up a huge part of purchases and most current profitability.

LRCX is fourth as it has historically been the poster child for the memory industry and saw huge upside from memory’s spending spree in the last up cycles. That said, even Lam is seeing an upturn given TSMC’s huge uptick.

The stocks
We have been positive on the stocks in the semi equipment sector calling for strong upside prior to the quarterly reports and urging investors to get in before Lam was the first to report.

We had also suggested at the time that after the stocks had their run up due to the positive reaction of the turn in the down cycle to an up cycle that we would be inclined to take some money off the table.

We think that post Applied quarter that lightening up may be prudent.

We have seen a strong run up across the board in all the stocks. The stocks are at all time highs in many cases and at all time highs in P/E ratios in most all cases. This is despite the fact that the recovery will be weak and slow with memory still dead.

The market seems to be pricing into the stocks a normal rip roaring semiconductor recovery when in fact we have a half baked, foundry/logic only recovery without any clear sight lines to a full recovery.

We are also concerned that there is not another near term upside for the stocks until they report the current quarter. Though one could argue that the next upside surprise will be memory recovering but we feel that we are going into the seasonally weak Q1 when memory is at its normal nadir, so a memory recovery is several quarters away at a very minimum.

At this point given that the stocks are priced to perfection in a less than perfect environment we also have the macro risk of China and trade that still hangs over us. The China issue seems to have gotten marginally worse of late as the deal we thought we had now seems more elusive as the intellectual property transfer issues seems less than settled.

Applied has just hit an all time high, jumping almost 10% on well known “news” of a recovery. We have no problem taking some of our profits from the turn in the cycle off the table until we see a better upside/downside risk/reward profile. We think Applied remains a premier company in the space and put up a very good report however the valuation is a bit ahead of reality.

November 15, 2019August 22, 2024

2020 Semiconductor Foundry Landscape Update!

2020 Semiconductor Foundry Landscape Update!
by Daniel Nenni on 11-15-2019 at 6:00 am
Categories: China, Foundries, GlobalFoundries, Intel Foundry, Samsung Foundry, Semiconductor Services, TSMC
5 Comments

When I first started working with the foundries 25 years ago I would have never imagined that I would make a career out of it, which I most certainly have. Fortunately, I recognized early on that not only are the foundries the cornerstone of the semiconductor ecosystem, they are also a very important economic bellwether, absolutely.

When I first started, a fabless company could use four different foundries (TSMC, UMC, SMIC, and Chartered) in a reasonably compatible manner. Generally, TSMC would be first to a process node so everyone started there and moved chips to the cheaper foundries for 2^nd, 3^rd, and even 4^th source manufacturing. This was not really ideal for TSMC as they did all of the heavy process ramp work only to share the more profitable high volume manufacturing with competitors.

This all changed in 2011 at 28nm when TSMC followed Intel using High-k Metal (HKMG) gate-last technology. The other foundries followed Samsung in using a gate-first HKMG 28nm technology which did not yield as expected. TSMC then went on to dominate the 28nm node and has been dominant ever since.

The days of TSMC compatible processes are now long gone with the FinFET era and TSMC continues to lead the semiconductor industry with the first high volume manufacturing EUV FinFET implementation at 7nm, 6nm, and 5nm. TSMC will continue to use FinFET EUV technology at 3nm then move to GAA at 2nm. Samsung is still working on perfecting EUV at 7nm and 5nm before moving to GAA at 3nm. Intel 7nm will be EUV FinFETs but Intel 5nm will be horizontal nanosheets and CFETs for Intel 3nm . It is hard to bet against TSMC but I would not bet against Intel or Samsung either.

Bottom line: The foundry business is thriving as systems companies do even more of their own chips and continue to push innovation to the limits of the fabless semiconductor ecosystem.

One of the reports I rely on for my foundry expertise is the IC Foundry Almanac published by the GSA in cooperation with IC Insights. The 2020 (12^th) Edition is out now and it continues to reinforce my 20+ year belief that the foundries are in fact the cornerstone of the semiconductor industry.

The report itself can be purchased from the GSA Store. I have a copy so if you have questions I may be able to help in the comments section or contact GSA directly. It is definitely worth the price of admission if you really want to know what is happening inside the fabless semiconductor ecosystem. Here is the executive summary:

The importance of wafer foundries continues to grow in the integrated circuit industry. About 43% of worldwide IC sales to systems makers in 2019 were coming from products fabricated by third-party silicon foundry providers compared to 36% in 2014 and 24% in 2009. Foundry-made ICs are expected to account for more than 40% of total integrated circuit sales to systems makers through 2023, according to the 2020 edition of The Foundry Almanac, which is jointly produced by the Global Semiconductor Alliance (GSA) and IC Insights Inc. The 12th annual edition of The Foundry Almanac shows worldwide IC foundry sales increasing by a compound annual growth rate (CAGR) of 6.4% between 2018 and 2023. This foundry growth rate is

higher than the expected 4.8% CAGR for total IC sales in the same forecast period. Currently, pureplay foundry suppliers generate about 81% of total IC foundry sales with the remaining 19% coming from integrated device manufacturers (IDMs) that process wafers for other companies in addition to making their own products in internal fabs.

The first part of this report contains an overview of the semiconductor foundry segment, forecasts, and analysis of trends by IC Insights. Following the market forecast section, the GSA presents a summary of foundry wafer pricing trends and photomask costs based on industry survey results. This report also contains a listing of foundry-supplier information compiled by the GSA.

Among the key conclusions and highlights in The 2020 IC Foundry Almanac are:

Total IC foundry sales (by both pure-play foundries and IDMs) are estimated to declined 2% in 2019 to $69.6 billion after increasing 5% to reach a record-high $72.6 billion in 2018. The last time IC foundry sales dropped was in 2009, when the semiconductor industry was hit by a downturn year after the financial crisis in 2008 triggered a deep global recession. In 2019, foundry sales slid lower because of growing concerns about an economic slump, which cause system makers to reduce IC purchases, and by slower growth in China that was partly a result of its trade war with the U.S.
Foundry growth is expected to return in 2020 with total sales rising 6% and setting a new alltime high of $73.6 billion. Total foundry sales (by both pure-play and IDM suppliers) are forecast to grow 8% in 2021 and strengthen in the next two years to reach $96.6 billion in 2023.
Pure-play foundry sales in 2020 are projected to grow 8% to a record-high $60.8 billion after falling 2% in 2019 and rising 5% in 2018. Pure-play foundry sales are expected to grow by a CAGR of 7.0% between 2018 and 2023 to reach $81.2 billion, driven by strong demand from fabless IC companies, increased outsourcing by IDMs, and shipments of custom-designed integrated circuits to systems houses, such as Apple in the U.S. and Huawei in China.
Foundry revenues generated by IDMs making ICs for other companies are forecast to drop 2% in 2020 to $12.8 billion after declining about 2% in 2019 and growing 3% in 2018. IDM foundry sales are projected to rise by a CAGR of 3.1% in the 2018-2023 period to reach $15.4 billion in the final year of the forecast.
Wafer-fab process technology with minimum feature sizes below 40nm generated about 47% of pure-play foundry sales in 2019 (estimated at $26.8 billion). Process technology with minimum feature sizes of 40nm or greater accounted for 53% of total pure-play foundry revenue in 2019 (estimated at $29.7 billion). Pure-play foundry sales for ICs made with <40nm technology increased 5% in 2019, while revenue for devices made with ≥40nm processes declined by 8% in the year.
Capital expenditures by IC foundries (both pure-play and IDM suppliers) grew 7% in 2019 to an estimated $23.9 billion after falling 15% in 2018 from a record-high $26.4 billion in 2017. Foundry capex in 2019 is estimated to be the second highest level of spending in a year. In 2020, foundry capital spending is expected to show a modest 4-5% increase with some major pure-play foundry suppliers remaining cautious and keeping their capex flat in the year.
Foundry wafer-fab utilization rates slid lower in 2019 because of a slowdown in IC purchases due to increasing uncertainty about global economic growth in the year ahead. Fab-capacity utilization at the four largest pure-play IC foundries (TSMC, GlobalFoundries, UMC, and SMIC) collectively stood at an average of 82% in 2019, down from 89% in 2018 and 90% between 2015 and 2017. In 2019, the “Big 4” pure-play foundries increased their combined installed fab capacity by 4% to nearly 49.3 million 200mm equivalent wafers compared to about 47.6 million wafers in 2018.
Fabless customers are estimated to account for 66% of pure-play foundry revenue in 2019 with IDMs representing 15% and systems makers being 19% of total sales. In 2010, the sales split was 76% to fabless customers, 23% to IDMs, and just 1% to systems manufacturers. The share of systems makers directly buying foundry-made ICs has climbed with Apple using Samsung and TSMC to fabrication of its custom-designed processors in iPhones, iPads, and other products as well as some Chinese smartphone and end-equipment makers—like telecom giant Huawei—developing integrated circuits that are made by foundries.
Communications ICs represented an estimated 57% of total pure-play foundry sales in 2019, followed by 17% for “other” ICs (for such applications as automotive, industrial, and medical systems), 14% for computer ICs, and 12% for consumer-product ICs.
Customers based in the Americas accounted for 56% of estimated pure-play foundry sales in 2019, followed by those headquartered in the Asia-Pacific region at 32%, Europe at 6%, and Japan at 5% of the total. China’s share of the pure-play foundry market in 2019 is estimated at about 18%, which is four percentage points greater than the marketshare of customers in the rest of the Asia-Pacific region in the year.
Two Chinese chipmakers (SMIC and Huahong Group) are ranked among the top 10 IC foundries in 2019, based on dollar-sales estimates. In total, Chinese manufacturers accounted for an estimated 9.4% of worldwide pure-play foundry sales in 2019, down slightly from 9.6% in 2018. The marketshare of China’s pure-play foundries remains below the peak of 13.3% recorded in 2006 and 2007. Mainland Chinese companies in the pure-play foundry business are expected to have a marketshare of 10.3% in 2023.
Two IDMs (Samsung and Fujitsu) are among the top 13 IC foundry suppliers in 2019. The rest are pure-play foundries. Fujitsu is expected to fall out of the top ranking of foundries in 2020 after it sold the remaining majority interest in its 300mm fab in Japan to Taiwan-based UMC in the summer of 2019.
Worldwide IC foundry production capacity (at both pure-play and IDM foundries) grew by about 5% in 2019 to an estimated 80.4 million wafers (measured in 200mm equivalents). Pure-play foundry annual capacity grew by an estimated 5% to about 63.8 million wafers in 2019, while IDM foundry capacity increased 4% to an estimated 16.6 million 200mm-equivalent wafers in the year. The “Big 4” pure-play foundries (TSMC, GlobalFoundries, UMC, and SMIC) accounted for an estimated 61% of total IC foundry capacity in 2019. Total foundry capacity (at both pureplay suppliers and IDMs) is forecast to rise 4% in 2020 to about 84.0 million 200mm-equivalent wafers, followed by another 4% increase in 2021 to 87.7 million in that year.
Overall, 200mm wafer fabrication pricing gradually increased from the second quarter of 2018 continuing through the second quarter of 2019 resulting in a 10% increase YoY. Furthermore, 300mm wafer fabrication pricing was relatively stable during the same period with a 2% decrease YoY. This reflects the stable demand for devices at older technology nodes using 200mm size wafers compared to newer technology nodes using 300mm wafers affected by the global slowdown.
GSA’s Wafer Fabrication Pricing Survey results show that participants still rely on older process nodes to maintain market share, as 49% of the capacity needs are at or above the 130nm node. Participants are also reporting an increase in demand for capacity at nodes below 50nm with 33% of participants needing capacity at these nodes compared to 24% last year.
200mm mask costs per layer remained flat throughout 2018. 300mm mask costs per layer, driven by the 28nm node, increased throughout 2018, continuing through the second quarter of 2019. This could be driven by the increase in complexity of the designs run on 300mm wafers.
With the downturn in 2019, wafer fabrication capacity became more available, which was reflected by the outlook of GSA survey participants. 82% of GSA’s 200mm wafer fabrication survey participants and 70% of 300mm wafer fabrication survey participants are forecasting that wafer fabrication pricing will be trending lower in the next 6 months.

November 6, 2019January 3, 2020

Calibre Commences Cloud Computing

Calibre Commences Cloud Computing
by Tom Simon on 11-06-2019 at 10:00 am
Categories: EDA, Siemens EDA, TSMC

Calibre was a big game changer for DRC users when it first came out. Its hierarchical approach dramatically shortened runtimes with the same accuracy as other existing, but slower, flat tools. However, one unsung part of this story was that getting Calibre up and running required minimal effort for users. Two things are required for people to change what they are doing and adopt a new approach. The advantages of making the change must be extremely compelling. And, the effort required to make the change must be minimized so that it is not difficult or problematic. Otherwise, people will gladly just keep on doing what they are used to. Mentor knew this then and they apparently still are keenly aware of it now.

Calibre in the Cloud is what Mentor calls their recent announcement regarding running Calibre in a cloud environment. In a technical brief written by Omar El-Sewefy, they discuss several advantages of running in a cloud environment. The main and obvious advantage is scalability. Cloud server offerings usually have the ability to scale up to impressively large numbers of processors. With this scalability comes the potential for higher throughput and the ability to handle peak loads without having to build massive infrastructure in-house. For many organizations DRC checks are infrequent but represent demanding loads on server resources, making cloud computing an attractive option.

However, users do not want to spend excessive time to configure and set up for cloud usage. Mentor laid the foundation for Calibre in the Cloud back in 2006 when they introduced Calibre hyper-remote capability. This let users run on very large numbers of processors to get a significant performance and capacity boost. The process for running in the cloud is very similar to a non-cloud run, minimizing the effort required to set up and run.

The technical brief covers three topics that make cloud runs fast and efficient. They have worked closely with foundries to make sure that the most recent rule decks make the best use of Calibre’s advanced features. As a result, even with increasing rule complexity and data set size, runtimes and memory utilization have remained steady or decreased.

Transporting the data to the cloud is optimized by moving the cells individually, not the flattened design, in what Mentor calls a hierarchical filing methodology. Of course, Calibre needs to assemble the entire design in order to work on it in the cloud. This step is called hierarchical construction mode, where the hierarchical data base (HDB) is created. In prior versions of Calibre, they would allocate and start the worker processes and have them wait for the HDB construction step. In a cloud environment it is more efficient to allocate processes when they are needed. So, one of the key changes in Calibre is called MTFlex, which optimizes CPU utilization so idle processors are not running when they are not needed.

Calibre in the Cloud uses regular licenses so there are no complications from that perspective. Also results and reports can be brought back for viewing in the same way as local runs. Overall Mentor has endeavored to make the entire operation as efficient and smooth as possible. Users can run locally if they want, and then quickly transition to the cloud when production load warrants it.

The technical brief entitled Calibre in the Cloud: Unlocking Massive Scaling and Cost Efficiencies is pretty interesting reading, and makes the point that close collaboration between customers, foundries, cloud providers and Mentor was necessary to deliver a robust solution for scaling by moving to the cloud. Also, at the TSMC OIP Forum in Santa Clara recently Mentor, Microsoft, TSMC and AMD jointly presented the results of using Calibre in the Cloud on a 500M gate design. The presentation on this case study is viewable on demand.

Interestingly running Calibre in the cloud can be an effective solution for large or small companies. Each has their own obstacles to running in periods of peak resource needs. The technical brief can be downloaded from the Mentor website for a full reading.