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Dolphin Webinar “The proven recipe for uLP SoC”

Dolphin Webinar “The proven recipe for uLP SoC”
by Eric Esteve on 11-11-2016 at 12:00 pm

Dolphin will hold a live webinar on November 15, 9:00 AM PST or November 22, 10:00 AM GMT. This webinar targets the SoC designers wanting to learn how to quickly implement ultra-low power (uLP) techniques, using proven recipes.

Chip designers are more and more involved in the design of connected devices, most often battery powered, and one of the main goals is to drastically decrease the chip power consumption. A few years ago, the race for high performance at reasonable cost was the main goal, except for the teams designing for wireless mobile applications. Many chip-makers have to adapt their design practices to the challenge of designing for low power, and even for ultra-low power. How to efficiently implement these new design techniques while staying on line with time-to-market (TTM) requirements?

This webinar will propose a step by step method for the adoption of more complex SoC architectures based on multiple power domains, which also require embedding the whole power regulation network. Dolphin will explain the rigorous methodology based on the step-wise analysis of the 4 intertwined embedded SoC networks: functional, clock, power regulation and mode control. The approach may look theoretical, but is very practical as for each network you can associate a set of silicon IP solutions that the designer could implement.

For the functional part of the circuit, you will implement the power gating of any power island or domain by using CLICK (the power island kit). As well the DELTA library of voltage regulators and monitors will be used to build the power regulation network of the SoC. Dolphin will present that is called “SoC Fabric IP” and which is a set of IP (voltage regulators, clock generators, monitors,…) allowing to implement a pre-defined embedded control network. The designer could develop a monolithic and full custom Activity Control Unit (ACU) or Power Management Unit (PMU / PMU logic), but such an homemade control network is known to be complex to develop, tedious to validate and little amenable to architectural updates.

When deciding to select the Dolphin’s solution, you are not only dealing with the make vs buy question. Designing a power aware SoC architecture significantly increase design complexity, impacting development schedule and cost, and could jeopardize the project if you miss the TTM window.

Dolphin is a well-known ASIC design service company for their mixed-signal design expertise and they know that dynamically switching the power domains on and off can lead to severe noise issues. Selecting a proven pre-defined embedded control network instead of designing it from scratch can dramatically increase the level of confidence in your SoC design noise immunity.

I have started my career as a PhD at Matra Harris Semiconductor in 1984 and I remember SAJI VA, our advanced analog technology (1 metal level, 2 poly, 2 or maybe 3 micron), and Dolphin, founded in 1985, was one of the first customers to use it. When you deal with analog or mixed-signal design, experience is really making the difference.

Designing for ultra-low power will become the mantra for many of the new SoC designs, but the related SoC architecture can be very complex to handle. If the design team has to develop a monolithic and full custom Activity Control Unit (ACU) or Power Management Unit, he will certainly make it eventually. But doing so is like re-inventing the wheel, with the risk of falling in traps impacting the design schedule, the development cost and the time-to-market. In the worst case, the design integrity can be impacted by poor noise immunity, leading to a redesign.

Make or buy is the project manager choice, but if you decide to ask for an expert advice before jumping start an uLP SoC design, attending this webinar from Dolphin may be wise…

Dolphin Integration has proven the effectiveness of this structured design methodology ensuring IP compatibility with its Taishan demochip designed in partnership with TSMC at 55 nm uLP eF.

If the following questions come to your mind, you will certainly benefit from this transfer of know-how:

  • How much reduction may I get from designing a SoC partitioned in multiple power domains?
  • Which approach is the most efficient for budgeting power consumption of my SoC?
  • Which new issues (noises…) should I be aware of to succeed the design of my ultra-low power SoC? What are the solutions to deal efficiently with these issues?
  • How can I maintain reasonable Time-to-Market while adopting advanced design methodologies?

To register, use this webinar link

Who should attend?

If you want to decrease your SoC power consumption but you feel that a SoC architecture based on power domains is too complex or un-tractable, this free webinar is made for you!

This webinar is for SoC architects, logic and analog designers as well project leaders. It provides tricks & tips for the design of ultra low-power consumption SoC with multiple power domains, starting from the SoC architecture down to the GDSII implementation.

Date and Time

This webinar occurs several times. Please register for the date and time that works best for you

[table]
|-
| style=”width: 307px” | Session 1: November 15, 2016

  • 9:00 AM for California, US
  • 12:00 PM for New-York, US
  • 5:00 PM for London, UK
  • 6:00 PM for Paris, France

|-
| style=”width: 307px” | Session 2: November 22, 2016

  • 10:00 AM for Paris, France
  • 11:00 AM for Tel-Aviv, Israel
  • 01:30 for New-Delhi, India
  • 04:00 PM for Shanghai, Beijing, China – Taipei, Taiwan
  • 07:00 PM for Seoul, South Korea

|-

Total Duration: 60 minutes
Presentation – 40 minutes
Live Q&A session – 20 minutes

By Eric Esteve from IPNEST