Accelerating Simulation. Innovation in VerificationFollowing a similar topic we covered early last…Read More
CEO Interview with Dr. Dennis Michaelis of GEMESYSDr. Dennis Michaelis is the founder and CEO…Read More
Consumer memory slowing more than AI gainingConsumer memory slowing more than AI gaining causing…Read More
One of the challenges with today’s SoCs is that chip-finishing, putting the final touches to the SoC working at the chip level, stresses layout editors to the limit. Either they run out of capacity to load the entire chip, or they can handle the entire chip but everything is like wading through molasses, it takes an awfully … Read More
What if Amazon’s new Kindle Fire, priced at $199 and using a sub $10 TI processor, has effectively started the ball rolling towards forcing Intel and AMD to building a Very Low Cost (perhaps even <$10) x86 mobile processor? A recent article entitled “Amazon’s Risky Strategy” explores the ramifications of Amazon selling Kindle… Read More
My last IC design at Intel was a Graphics Chip and I developed a layout generator for Programmable Logic Arrays (PLA) that automated the task, so I’ve always been interested in how to make IC layout more push-button and less polygon pushing. Today I watched a video about HiPer DevGen from Tanner EDA and wanted to share what I … Read More
Some call it co-opetition (collaborative competition), some call it keeping your enemies close. Others call it for what it is, unfair competition and/or other types of legally actionable behavior. GlobalFoundries calls it“Fab Syncing”, which in reality will SINK their FABS!
“With this new collaboration, we are making one … Read More
During the weekend, I read two articles that highlighted Apple’s LCD supply chain build out and started to think of how this would look if Apple were to do the same on the x86 side of the ledger. The two articles, one related to Hitachi and Sony building a new 4” LCD for iphones and a more extensive one on Sharp building a new LCD for the iPAD3… Read More
I’ve blogged about the Calibre family of IC design tools before:
Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is Better… Read More
When AMD announced its cutbacks recently many people were left wondering why they were so deep given the strong financial performance in Q3 and the guidance for an up Q4. It couldn’t have been related to the Thailand floods that could have been at most a one-quarter squeeze expected in Q1. Now it is apparent from reports that AMD’s … Read More
Interesting story, for my wife’s 50th birthday we went to Las Vegas to see Sir Elton John in concert. My wife is an Elton fan and this may be her last chance to see him live so off we went. I saw Elton and Billy Joel in a dueling piano concert a while back and it was simply amazing! The underlying purpose of the trip however was to earn “Perfect… Read More
Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. Sgroi et al. call “the layered-stack approach to the design of the on-chip intercore communications the Network-on-Chip (NOC) methodology.” In a NoC system, modules such as processor… Read More
Flash analog-to-digital converters (ADCs) are commonly used in high-frequency applications such as satellite communications, sampling oscilloscopes, and radar detection. Flash ADC is preferred over other ADC architectures because it is extremely fast and quite simple. However, flash ADC typically requires twice as many… Read More
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CES 2025 and all things Cycling