Events EDA2025 esig 2024 800X100

TSMC Gets Fooled Again!

TSMC Gets Fooled Again!
by Daniel Nenni on 10-16-2011 at 2:51 pm

If you follow the SemiWiki Twitter feed you may have noticed that The Motley Fool (Seth Jayson) did three more articles on TSMC financials. The first Foolish article was blogged on SemiWiki as “TSMC Financial Status and OIP Update”.

The next three Fool Hardy articles look at cash flow (the cash moving in and out of a business), accounts… Read More


Austin and San Jose SCC

Austin and San Jose SCC
by Paul McLellan on 10-14-2011 at 3:35 pm

Don’t forget the SpringSoft Community Conferences next week in Austin on Tuesday and in San Jose on Thursday. There is no charge and you even get a free lunch (see “no such thing as…”).

The morning in Austin is focused on functional closure and how to leverage SpringSoft’s verification technology… Read More


Soft IP Qualification

Soft IP Qualification
by Paul McLellan on 10-14-2011 at 3:10 pm

At the TSMC Open Innovation Platform Ecosystem Forum (try saying that three times in a row) next week (on Tuesday 18th), Atrenta will present a paper on the TSMC soft IP qualification flow. It will be presented by Anuj Kumar, senior manager of the customer consulting group.

More and more, chips are not put together what we think of … Read More


Conclusion of the USB 3.0 IP forecast from IPNEST… complimentary for SemiWiki readers

Conclusion of the USB 3.0 IP forecast from IPNEST… complimentary for SemiWiki readers
by Eric Esteve on 10-14-2011 at 10:40 am

Using the “Diffusion of Innovation” theory, we have built a forecast for the market of USB 3.0 IP in 2011-2015. In this new version of the report, we have inserted the actual revenues generated by USB 3.0 IP from different vendors, for 2009 and 2010, and reworked the 2011-2015 forecast. Initially, we had expected this IP market to … Read More


FPGA Prototyping – What I learned at a Seminar

FPGA Prototyping – What I learned at a Seminar
by Daniel Payne on 10-14-2011 at 10:11 am

Intro
My first exposure to hardware prototyping was at Intel back in 1980 when the iAPX 432 chip-set group decided to build a TTL-based wire-wrap prototype of a 32 bit processor to execute the Ada language. The effort to create the prototype took much longer than expected and was only functional a few months before silicon came back.… Read More


From IBM Mainframes to Wintel PCs to Apple iPhones: 70% is the Magic Number

From IBM Mainframes to Wintel PCs to Apple iPhones: 70% is the Magic Number
by Ed McKernan on 10-12-2011 at 10:51 am

Time to ring the Bell. With the iPhone 4S, Apple has just surpassed the 70% gross margin metric that usually equates to a compute platform becoming an industry standard. IBM’s mainframe achieved it in the 1960s with the 360 series and still is able to crank it out with their Z-series. The combined Intel and Microsoft tandem (Wintel)… Read More


A New Name: ‘Si2Con’ Arrives October 20th!

A New Name: ‘Si2Con’ Arrives October 20th!
by Daniel Nenni on 10-11-2011 at 7:58 pm

In case you have not heard, the 16th Si2-hosted conference highlighting industry progress in design flow interoperability comes to Silicon Valley (Santa Clara, CA) on October 20th. Si2Con will showcase recent progress of members in the critical areas of:

[LIST=1]

  • Design tool flow integration (OpenAccess)
  • DRC / DFM / Parasitics
  • Read More

    Global Semiconductor Alliance Ecosystem Summit Trip Report!

    Global Semiconductor Alliance Ecosystem Summit Trip Report!
    by Daniel Nenni on 10-10-2011 at 7:06 pm

    Being an internationally recognized industry blogger (IRIB) does have its benefits, one of which is free invites to all of the cool industry conferences! The presentations are canned for the most part but you can learn a lot at the breaks and exhibits if you know the right questions to ask, which I certainly do.

    The GSA Semiconductor
    Read More


    Mask and Optical Models–Evolution of Lithography Process Models, Part IV

    Mask and Optical Models–Evolution of Lithography Process Models, Part IV
    by Beth Martin on 10-10-2011 at 4:50 pm

    Will Rogers said that an economist’s guess is liable to be as good as anyone’s, but with advanced-node optical lithography, I might have to disagree. Unlike the fickle economy, the distorting effects of the mask and lithographic system are ruled by physics, and so can be modeled.

    In this installment, I’ll talk about two critical… Read More


    Solido & TSMC Variation Webinar for Optimal Yield in Memory, Analog, Custom Digital Design

    Solido & TSMC Variation Webinar for Optimal Yield in Memory, Analog, Custom Digital Design
    by Daniel Nenni on 10-09-2011 at 4:01 pm

    Solido has announced webinars for North America, Europe and Asia on October 12-13. They will be describing the variation analysis and design solutions in the TSMC AMS Reference Flow 2.0 announced at the Design Automation Conference this year.

    “We are pleased to broaden our collaboration with Solido in developing advanced variation… Read More