At the TSMC Open Innovation Platform Ecosystem Forum (try saying that three times in a row) next week (on Tuesday 18th), Atrenta will present a paper on the TSMC soft IP qualification flow. It will be presented by Anuj Kumar, senior manager of the customer consulting group.
More and more, chips are not put together what we think of as the standard way, by writing a bunch of RTL and then going through “classic” EDA. Instead, they are assembled out of pre-existing IP, either from the 3rd party IP marketplace or from a previous chip in the same company. So the focus of what is important in a design has to change. On many chips the IP content is well over 80%, and a lot of that is in the form of soft IP blocks (aka synthesizable IP). So it is essential that designers know the quality of the IP and any integration risks associated with using it. This information is crucial to making sure that an SoC meets its power, performance, area (price) and schedule.
Atrenta has been collaborating with TSMC to create a comprehensive system to automate the process of IP qualification. Of course this is based on the SpyGlass platform. The system analyzes soft IP using an IP handoff methodology consisting of TSMC’s Golden Rule Set covering various design parameters for the soft IP block: risk analysis, integration readiness, implementation readiness and reusability.
Information on the TSMC Open Innovation Platform Ecosystem Forum is here. Atrenta will be presenting at 1pm on Tuesday October 18th.Share this post via: