Codasip at the 2024 Design Automation ConferenceCodasip will be demonstrating its new L110 core…Read More
Siemens Hardware-Assisted Verification at the 2024 Design Automation ConferenceVisitors to Siemens’ booth (#2521) at the 61st…Read MoreVerific at the 2024 Design Automation ConferenceVerific Design Automation will host two well-funded AI…Read MoreSmartDV at the 2024 Design Automation ConferenceSmartDV’s presence at 61st DAC centers on connections,…Read MoreBlue Pearl Software at the 2024 Design Automation ConferenceTwenty years ago, Blue Pearl showcased its first-generation…Read More
If you just casually peruse most marketing presentations by EDA companies, you’d come to the conclusion most SoCs are designed from scratch, wrestlilng the monster to the ground with bare hands. But the reality is that most SoCs consist of perhaps 90% IP blocks (many of them memories). That still leaves the remaining 10% … Read More
Hard to believe a year has gone by since the big announcement of the Cadence Blueprint toBattle ‘Profitability Gap’; Counters Semiconductor Industry’s Greatest Threat! Having spent more time on it that I should have, here is my opinion on EDA360 on its first anniversary.
Richard Georing did a very nice anniversary piece “Ten Key… Read More
The problem:To move dual-port SRAM library and macros from a 40nm process to a 28nm process. In addition to all the changes between two different foundry processes, the 28nm rules are disruptive and incompatible with the previous rules. The memory corecells (foundry-specific) would also need to be completely replaced.
Current… Read More
Intel had a big press event yesterday at which they announced details of their 22nm process. In a change from their current processes, it goes with a vertical gate. In fact 3 gates which gives them much better control of leakage through transistors that are switched off, along with more transmission through the on transistors. They… Read More
As the complexity of the chip-package-system (CPS) interactions has increased, the tradeoffs in doing a power and noise analysis has had to gradually increase. As is so often the case in semiconductor designs, issues first arise as second-order effects that can largely be ignored but each process node makes the problem worse … Read More
DAC is less than a month away, June 6-8th for the tradeshow, longer depending on what other events you might also be attending. Apache is in booth 2448 (marked in red on the DAC floorplan map.
Many of the presentations at the Apache booth will be customers (such as ARM, Xilinx, ST Ericsson, GlobalFoundries and TSMC) discussing various… Read More
Introduction
Today Cadence announced at the Embedded Systems Conference something of interest to systems designers.
What’s New?
The Rapid Prototyping Platform and Virtual System Platform are what’s new, and they intend to enable and automate concurrent hardware and software development. I can remember Mentor… Read More
Although there has been always a strong relationship between Kilopass and Chartered Semiconductor, this relationship has been even enhanced after the acquisition of Chartered by GLOBALFOUNDRIES, allowing Kilopass’s customers to integrate NVM IP on advanced technology nodes, down to 40nm or even 28nm in the near future.
Before… Read More
Introduction
IC designs go through a layout process and then a verification of that layout to determine if the layout layer width and spacing rules conform to a set of manufacturing design rules. Adhering to the layout rules will ensure that your chip has acceptable yields.
At the 28nm node a typical DRC (Design Rule Check) deck will… Read More
The corporate raiders are still throwing rocks at Mentor Graphics. I have followed this reality show VERY closely and find their latest assault seriously counterproductive. Disinformation is common in EDA but I expected more from Carl Icahn and the Raiderettes. They are quite the drama queens. Here is a billion dollar question:… Read More
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