800x100 Efficient and Robust Memory Verification (2)

IP-SoC 2011: prepare the future, what’s coming next after IP based design?

IP-SoC 2011: prepare the future, what’s coming next after IP based design?
by Eric Esteve on 12-03-2011 at 2:58 am

IP-SoC 2011is the 20[SUP]th[/SUP] anniversary for the first Conference completely dedicated to IP. IP market is a small world, as EDA a small market if you look at the generated revenue… but both are essential building blocks for the semiconductor industry. It was not clear back in 1995 that IP will become essential: at that time,… Read More


It’s not just handsets

It’s not just handsets
by Paul McLellan on 11-30-2011 at 7:58 pm

I usually write about the handset business (terminals in wireless-speak) because it is a consumer business and drives, directly and indirectly, a large part of the semiconductor business. But there is another part to the business, base-stations.

The largest supplier of wireless networking equipment is Ericsson. Ericsson … Read More


Synopsys acquires Magma

Synopsys acquires Magma
by Paul McLellan on 11-30-2011 at 4:41 pm

So Synopsys announced today that it has signed an agreement to acquire Magma. There will be a regulatory delay etc before it finally closes.

So why did they do it? Despite Magma being thought of as a place and route company, they have two other product that are perhaps more significant for Synopsys: FineSim and Tekton.

FineSim, Magma’s… Read More


100 USB 3.0 IP Design-In…Is PLDA rocketing SuperSpeed USB technology?

100 USB 3.0 IP Design-In…Is PLDA rocketing SuperSpeed USB technology?
by Eric Esteve on 11-29-2011 at 10:19 am

Did we (the analyst) completely underestimate SuperSpeed USB take-off, or is the company tweaking the meaning of “USB 3.0 IP Design-In”? This PRfrom PLDA could be understood as a claiming from the IP vendor that they have achieved the 100[SUP]th[/SUP] design win for their USB 3.0 IP… Let’s try to understand how PLDA can make more… Read More


Blitz, blazing fast layout

Blitz, blazing fast layout
by Paul McLellan on 11-29-2011 at 8:00 am

One of the challenges with today’s SoCs is that chip-finishing, putting the final touches to the SoC working at the chip level, stresses layout editors to the limit. Either they run out of capacity to load the entire chip, or they can handle the entire chip but everything is like wading through molasses, it takes an awfully … Read More


Will Amazon’s Kindle Fire Force x86 Processors To Revisit the 1980s?

Will Amazon’s Kindle Fire Force x86 Processors To Revisit the 1980s?
by Ed McKernan on 11-29-2011 at 12:07 am

What if Amazon’s new Kindle Fire, priced at $199 and using a sub $10 TI processor, has effectively started the ball rolling towards forcing Intel and AMD to building a Very Low Cost (perhaps even <$10) x86 mobile processor? A recent article entitled “Amazon’s Risky Strategy” explores the ramifications of Amazon selling Kindle… Read More


A Review of an Analog Layout Tool called HiPer DevGen

A Review of an Analog Layout Tool called HiPer DevGen
by Daniel Payne on 11-28-2011 at 1:11 pm

My last IC design at Intel was a Graphics Chip and I developed a layout generator for Programmable Logic Arrays (PLA) that automated the task, so I’ve always been interested in how to make IC layout more push-button and less polygon pushing. Today I watched a video about HiPer DevGen from Tanner EDA and wanted to share what I … Read More


GlobalFoundries Versus Samsung!

GlobalFoundries Versus Samsung!
by Daniel Nenni on 11-27-2011 at 7:00 pm

Some call it co-opetition (collaborative competition), some call it keeping your enemies close. Others call it for what it is, unfair competition and/or other types of legally actionable behavior. GlobalFoundries calls it“Fab Syncing”, which in reality will SINK their FABS!

“With this new collaboration, we are making one Read More


Did Apple Influence AMD’s TSMC Foundry Switch?

Did Apple Influence AMD’s TSMC Foundry Switch?
by Ed McKernan on 11-27-2011 at 7:00 pm

During the weekend, I read two articles that highlighted Apple’s LCD supply chain build out and started to think of how this would look if Apple were to do the same on the x86 side of the ledger. The two articles, one related to Hitachi and Sony building a new 4” LCD for iphones and a more extensive one on Sharp building a new LCD for the iPAD3… Read More


December 1st – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)

December 1st – Hands-on Workshop with Calibre: DRC, LVS, DFM, xRC, ERC (Fremont, California)
by Daniel Payne on 11-24-2011 at 9:57 am

I’ve blogged about the Calibre family of IC design tools before:

Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is BetterRead More