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Such a small piece of Silicon, so strategic PHY IP

Such a small piece of Silicon, so strategic PHY IP
by Eric Esteve on 04-30-2012 at 6:05 am

How could I talk about the various Interface protocols (PCIe, USB, MIPI, DDRn…) from an IP perspective and miss the PHY IP! Especially these days, where the PHY IP market has been seriously shaken, as we will see in this post, and will probably continue to be shaken… but we will have to wait and look at the M&A news during the next … Read More


GSA 3DIC and Cadence

GSA 3DIC and Cadence
by Paul McLellan on 04-29-2012 at 10:00 pm

At the GSA 3D IC working group meeting, Cadence presented their perspective on 3D ICs. Their view will turn out to be important since the new chair of the 3D IC working group is going to be Ken Potts of Cadence. Once GSA decided the position could not be funded then an independent consultant like Herb Reiter had to bow out and the position… Read More


Smart mobile SoCs: Apple

Smart mobile SoCs: Apple
by Don Dingee on 04-29-2012 at 9:00 pm

Apple sells devices. Lots of them. Their success is due to many things related to design and tech religion, and an important part is the SoC inside those devices which creates the experience people want. The official Apple information on their parts is minimal. Their SoCs have been dissected with more fervor than Roswell aliens.… Read More


A Simple, Scalable LDE Optimization Flow for 28/20nm Custom/AMS Design

A Simple, Scalable LDE Optimization Flow for 28/20nm Custom/AMS Design
by Eric Filseth on 04-29-2012 at 9:00 pm

At 28nm and below, a number of electrical variation effects become significant which depend not only on individual devices, but the physical interaction between neighboring devices, wells, etc during the manufacturing process. Some of these effects have become collectively referred to as “Layout Dependent Effects” (LDE);… Read More


Intel says fabless model collapsing… really?

Intel says fabless model collapsing… really?
by Daniel Nenni on 04-28-2012 at 7:00 pm

There is an interesting discussion in the SemiWiki forum in response to the EETimes article: Intel exec says fabless model ‘collapsing’. Definitely an interesting debate, one worth our time since the advertising click hungry industry pundits will certainly jump all over it. Clearly I’m biased since I helped build… Read More


IC Reliability and Prevention During Design with EDA Tools

IC Reliability and Prevention During Design with EDA Tools
by Daniel Payne on 04-27-2012 at 5:04 pm

IC device physics uncovers limits to reliable operation, so IC designers are learning to first identify and then fix reliability issues prior to tape-out. Here’ s a list of reliability issues to keep you awake at night:… Read More


Next Generation Transistors

Next Generation Transistors
by Paul McLellan on 04-27-2012 at 1:54 pm

We have all heard that planar transistors have run out of steam. There are two ways forward. The one that has garnered all the attention is Intel’s trigate which is their name for FinFET. The other is using thin film SoI which ST is doing. TSMC and Global seem to be going the FinFET way too, although at a more leisurely pace. But … Read More


Keeping Moore’s Law Alive

Keeping Moore’s Law Alive
by Paul McLellan on 04-27-2012 at 12:37 pm

At the GSA silicon summit yesterday the first keynote was by Subramanian Iyer of IBM on Keeping Moore’s Law Alive. He started off by asking the question “Is Moore’s Law in trouble?” and answered with an equivocal “maybe.”

Like some of the other speakers during the day, he pointed out that … Read More


Introduction to FinFET technology Part II

Introduction to FinFET technology Part II
by Tom Dillinger on 04-27-2012 at 9:00 am

The previous post in this series provided an overview of FinFET devices. This article will briefly cover FinFET fabrication.

The major process steps in fabricating silicon fins are shown in Figures 1 through 3. The step that defines the fin thickness uses Sidewall Image Transfer (SIT). Low-pressure chemical vapor (isotropic)… Read More


Kadenz Leben: CDNLive! EMEA

Kadenz Leben: CDNLive! EMEA
by Paul McLellan on 04-27-2012 at 2:01 am

If you are in Europe then the CDNLive! EMEA user conference is in Munich at the Dolce Hotel from May 14th to 16th. Like last month’s CDNLive! in Cadence’s hometown San Jose, the conference focuses on sharing fresh ideas and best practices for all aspects of semiconductor design from embedded software down to bare silicon.… Read More