This is obviously great news for SilabTech, and this is the type of news which will change the perception that we (non-Indian) have of the Semiconductor industry in India. About 15-20 years ago, the India Embedded/VLSI industry was perceived as low cost design resource pool, a good place where to implement design center. The hidden… Read More
NIST Sets a Clearer Course for the Post-Quantum Security TransitionNIST’s report, Transition to Post-Quantum Cryptography Standards, gives…Read More
CTO Interview with Ed Plowman of Imagination TechnologiesEd Plowman is Chief Technology Officer at Imagination…Read More
Ceva’s next NeuPro generation opens new possibilities across AICeva is broadening the possibilities for AI silicon…Read More
How Allegro MicroSystems Increased OEE by Several Percentage Points with yieldHUB LiveAllegro MicroSystems’ experience with yieldHUB Live shows how…Read More
Interview with Sweta Gupta, VP of Engineering of Analog BitsSweta Gupta is the Vice President of Engineering…Read More
Intel is NOT Transparent Again!
Recent headlines suggest that Intel was not transparent about some of the products they showed at the CES keynote. Intel confirmed on Friday that they used ARM-based chips for some of the products but would not say which ones. When your company’s tag line is “Intel Inside” and you hold up a product during your keynote wouldn’t… Read More
Managing Heat for System Reliability
In most of the electronic equipments, semiconductor chips are a major source of heat generation. And in semiconductor designs several hardware and software techniques are being used to contain power dissipation; a major cause for heat. However due to multiple functionality being squeezed into small form factors, we continue… Read More
JasperGold COV App, the Swiss Army Knife for Verification
At the Jasper Users Group meeting in October Rajeev Ranjan presented on the JasperGold COV App which he described as the Swiss army knife for verification. It comes in many sizes and contains many useful tools.
The primary goal of COV is to provide coverage metrics:
- stimuli coverage: how restrictive is the design behavior under
Handel Jones Predicts Process Roadmap Slips
At the SEMI ISS conference earlier this week, the last speaker in the technology challenges section was Handel Jones of IBS. I’ve known Handel since the mid-1980s when he came to VLSI Technology and told us we were losing money on 90% of the designs we were doing but our cost model was not good enough and so we didn’t even… Read More
Positive Semiconductor Job Outlook in 2014!
Based on local traffic patterns and my experience in Silicon Valley over the last 30 years we are looking at a much higher employment rate inside the fabless semiconductor ecosystem, absolutely. Jobs are being filled more so than I have seen in the past ten years. The challenge of course is finding the right people for the right job… Read More
International CES Wrapup
Semiconductor Intelligence attended the International CES last week in Las Vegas, Nevada. A wide variety of consumer electronics devices were displayed at the conference. These ranged from:
· Fascinating – but is it practical? (personal robots, drones)
· Exciting – but when will it be cheap enough for the mass market? (UHD TV,… Read More
MIPI Alliance Specifications Adoption Status in 2013
At the beginning of December in Paris I had the opportunity to make a presentation to a very impressive audience, technical gurus from companies contributing to MIPI Alliance specification were here, including ST-Microelectronics, Intel, Qualcomm, TI, Toshiba, Nokia, Samsung, to name a few. … Read More
Is Intel the Concorde of Semiconductor Companies?
An Intel executive recently told me that my Intel articles on SemiWiki are used to motivate employees to work hard and prove me wrong. The converse is also true. The senseless Intel fabless ecosystem bashing motivates me to continue to write so it is a win-win scenario, absolutely. In fact, I should credit Intel’s Mark Bohr… Read More
The State of 450mm Wafers. And Intel Gossip
Paul Farrar, the General Manager of the Global 450mm Consortium (G450C) presented at the SEMI ISS conference today. What is G450C, it is a public-private consortium to develop a cost-effective 450mm wafer fabrication infrastructure, develop equipment prototypes and coordinate the industry move to 450mm. It is located in Albany… Read More
The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival