The Network On Chip (NoC) concept is recent, about 10 years old, and the first implementation of commercially available NoC IP has happened in 2006. Should we drop the concept so quickly after it has been introduced? In fact, I don’t think so… But we could brain storm and imagine the new functions that could be implemented within or… Read More





Schematic Migration Across Foundries and Processes
A dedicated schematic migration tool can save weeks of effort and allow companies to explore new foundry opportunities. Unfortunately moving analog and mixed signal design data between foundries and processes is a complex business. While engineers would rather spend their days creating new circuits, many spend time translating… Read More
Cadence IP Report Card 2013
The challenges of developing IP blocks, integrating them correctly, and hitting the power, performance, area, and time to market requirements of a mobile SoC is a growing problem. At 20nm and 14nm the probability of a chip re-spin due to an error is approaching 50% and we all know how disastrous a re-spin can be, those are not good … Read More
Plotting to take over the time-domain only world
The state machine nature of many digital designs has made time-domain debugging the favorite tool for most designers. We provide a set of inputs, data gets clocked in, and a set of outputs appears. We look for specific patterns in parallel paths, or sequences on serial lines.… Read More
EDAC CEOs: consolidation, clouds, and whether Intel will buy Synopsys
Yesterday evening was the annual EDAC CEO forecast meeting. Actually it is not really a forecast meeting any more, more a sort of CEO response to some survey questions asked of EDAC members. Rich Valera of Needham moderated with Lip-Bu, Aart and Wally, along with Simon Segars representing the IP arm(!) of the business and Raul Camposano… Read More
Visual Debugging at Altera on Billion-Transistor Chips
My first job out of college was doing transistor-level circuit design, so I’m always curious about how companies are doing billion-transistor chip design and debug these days at the FPGA companies.
I spoke with Yaron Kretchmer,he works at Altera and manages the engineering infrastructure group where they have a compute… Read More
Can “Less than Moore” FDSOI provides better ROI for Mobile IC?
In this previous article, I was suggesting that certain chip makers may take a serious look at a disruptive way to look at Moore’s law, as they may get better ROI, profit and even better revenue. The idea is to select technology node and packaging technique in order to optimize the Price, Performance, Power triptych and manage chip… Read More
Costello on Communicating a Compelling Company Story
The next EDAC sponsored emerging company series (what I’ve been calling Hogan University) is Joe Costello being interviewed on how to communicate a compelling company story. Anyone who saw Joe’s keynote at DAC several years ago will not want to miss this. I can’t promise that he’ll lie down on the stage… Read More
IJTAG for IP Test: a free seminar
What: Better IP Test with IJTAG
When: 26 March, 2013, 10:30am-1:30pm
Where: Mentor Graphics, 46871 Bayside Parkway, Fremont, CA 94538
If you are involved in IC test*, you’ve probably heard about the IEEE P1687 standard, called IJTAG for ‘internal’ JTAG. IJTAG defines a standard for embedded IP that includes simple… Read More
ARM Cortex SoC Prototyping Platform for Industrial Applications
If your next SoC uses an ARM Cortex-A9 and has an industrial application, then you can save much design and debug time by using a prototyping platform. The price to prototype is quite affordable, and the methodology has a short learning curve. Bill Tomasan Aldec Research Engineer conducted a webinar today on: ARM Cortex SoC Prototyping… Read More
TSMC N3 Process Technology Wiki