The challenges of developing IP blocks, integrating them correctly, and hitting the power, performance, area, and time to market requirements of a mobile SoC is a growing problem. At 20nm and 14nm the probability of a chip re-spin due to an error is approaching 50% and we all know how disastrous a re-spin can be, those are not good odds even in Las Vegas.
Cadence talked a bit about IP during the CDNLive keynotes last week and even more so during a press lunch. Paul McLellan and I also spent time with Cadence IP Commander in Chief Martin Lund. Given the recent IP acquisitions it is clear that Cadence is serious about scaling their business so I have to give them an A+ on IP strategy thus far.
My first meeting with Martin is referenced in Cadence IP Strategy 2012, I liked him then and after two most excellent acquisitions I love the man. Great for IP, great for EDA, Cadence is now the #3 IP company behind ARM and Synopsys.
Unfortunately, assembling a robust IP offering is the easy part especially when you have a CEO (Lip-Bu Tan) who can raise money in his sleep. Selling commercial IP into a consolidating industry however is much more of a challenge that you might think. In my best guesstimate 80% of today’s silicon is shipped by the top 20 semiconductor companies and that is being generous. It could be less than 20 companies and of the top 20 companies listed below only UMC and GLOBALFOUNDRIES do NOT have sizable internal IP groups.
Clearly Martin Lund knows this since he worked at Broadcom for 12+ years and Broadcom has a VERY large IP group. So what is the Cadence IP strategy moving forward? In my opinion it is two-fold: IP Subsystems, which explains the Tensilica acquisition, and FinFETs, which is what the Cosmic Circuits acquisition is all about.
Dr. Paul McLellan covers Tensilica HEREand Dr. Eric Esteve covers CEVA HERE for SemiWiki. Click on over to the landing pages and you will read all about IP subsystems because that is what they do. That is how they differentiate themselves from the mighty ARM.
Cosmic Circuits does foundation IP which is the connection between the interface IP and the semiconductor process technologies. FinFETs are changing the foundation IP world as we speak. For layout people, the F word now stands for FinFETs because FunFETs they are not. There is an interesting thread in the SemiWiki forum HERE which talks about the FinFET layout challenges ahead. Bottom line: Not everybody will be successful with FinFETs so adopting commercial foundation IP is much more viable if you want to hit the power, performance, area, and time to market requirements of mobile SoCs.
Given that the Cadence Virtuoso dynasty has a good 90% AMS market share (my opinion) and probably a 99.9% FinFET layout market share thus far, I give Cadence a real shot at moving some commercial IP into the 20% of the companies that are shipping 80% of the silicon. They certainly have access to the top 20 IP groups through Virtuoso and IP subsystems fit right on top of that. Sound reasonable?
For the best detailed coverage of the CDNLive keynotes see Richard Goering’s posts:
Lip-Bu Tan at CDNLive 2013: Opportunities and Challenges for Electronics
Samsung CDNLive Keynote: Innovation and Challenges in the Post-PC Era
Martin Lund CDNLive Keynote: Why SoCs Need “Application Optimized” IP