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EDAC CEOs: consolidation, clouds, and whether Intel will buy Synopsys

EDAC CEOs: consolidation, clouds, and whether Intel will buy Synopsys
by Paul McLellan on 03-15-2013 at 5:12 pm

Yesterday evening was the annual EDAC CEO forecast meeting. Actually it is not really a forecast meeting any more, more a sort of CEO response to some survey questions asked of EDAC members. Rich Valera of Needham moderated with Lip-Bu, Aart and Wally, along with Simon Segars representing the IP arm(!) of the business and Raul Camposano… Read More


Visual Debugging at Altera on Billion-Transistor Chips

Visual Debugging at Altera on Billion-Transistor Chips
by Daniel Payne on 03-15-2013 at 10:38 am

My first job out of college was doing transistor-level circuit design, so I’m always curious about how companies are doing billion-transistor chip design and debug these days at the FPGA companies.

I spoke with Yaron Kretchmer,he works at Altera and manages the engineering infrastructure group where they have a compute… Read More


Can “Less than Moore” FDSOI provides better ROI for Mobile IC?

Can “Less than Moore” FDSOI provides better ROI for Mobile IC?
by Eric Esteve on 03-15-2013 at 10:00 am

In this previous article, I was suggesting that certain chip makers may take a serious look at a disruptive way to look at Moore’s law, as they may get better ROI, profit and even better revenue. The idea is to select technology node and packaging technique in order to optimize the Price, Performance, Power triptych and manage chip… Read More


Costello on Communicating a Compelling Company Story

Costello on Communicating a Compelling Company Story
by Paul McLellan on 03-14-2013 at 11:53 pm

The next EDAC sponsored emerging company series (what I’ve been calling Hogan University) is Joe Costello being interviewed on how to communicate a compelling company story. Anyone who saw Joe’s keynote at DAC several years ago will not want to miss this. I can’t promise that he’ll lie down on the stage… Read More


IJTAG for IP Test: a free seminar

IJTAG for IP Test: a free seminar
by Beth Martin on 03-14-2013 at 1:53 pm

What: Better IP Test with IJTAG
When: 26 March, 2013, 10:30am-1:30pm
Where: Mentor Graphics, 46871 Bayside Parkway, Fremont, CA 94538


If you are involved in IC test*, you’ve probably heard about the IEEE P1687 standard, called IJTAG for ‘internal’ JTAG. IJTAG defines a standard for embedded IP that includes simple… Read More


ARM Cortex SoC Prototyping Platform for Industrial Applications

ARM Cortex SoC Prototyping Platform for Industrial Applications
by Daniel Payne on 03-14-2013 at 1:00 pm

If your next SoC uses an ARM Cortex-A9 and has an industrial application, then you can save much design and debug time by using a prototyping platform. The price to prototype is quite affordable, and the methodology has a short learning curve. Bill Tomasan Aldec Research Engineer conducted a webinar today on: ARM Cortex SoC PrototypingRead More


Synopsys ♥ TSMC!

Synopsys ♥ TSMC!
by Daniel Nenni on 03-14-2013 at 8:00 am

Dr. Paul McLellan and I will be covering the Silicon Valley SNUG live again this year. Unfortunately we are only allowed to see the keynotes (same thing with CDNLive) but they look very good:

Keynote Address: Massive Innovation and Collaboration into the “GigaScale” Age!
Aart de Geus, Chairman and co-CEO, Synopsys,
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Will next generation Mobile Devices support PCI Express? M-PCIe is coming fast!

Will next generation Mobile Devices support PCI Express? M-PCIe is coming fast!
by Eric Esteve on 03-14-2013 at 6:22 am

Those who have read the numerous articles I have written about MIPI, or PCIe, or the fusion of both named “Mobile Express” know my position: the question is not “Will Mobile devices support PCI Express?” but “When will we see Mobile devices integrating Mobile Express?” I was not really surprised by the Press Release that Cadence … Read More


Formal Verification of Power Intent

Formal Verification of Power Intent
by Paul McLellan on 03-13-2013 at 4:10 pm

I can’t imagine that any SoC today is designed without taking intense interest in how much power the chip will consume, whether it is destined for a mobile phone or tethered in a cloud datacenter. One challenge with power is that adding features like voltage islands or power-down areas require changes to the netlist such as… Read More


Margaret Butler: One Woman’s Life in Science

Margaret Butler: One Woman’s Life in Science
by Holly Stump on 03-13-2013 at 4:00 pm

46 years in Computing, 1945-1991

Margaret (Kampschaefer) Butler was a pioneer in technology, a ground-breaking woman who graduated with a B.S in Mathematics and Statistics in 1944, and followed a fascinating career path in the public sector starting in the earliest days of computers and nuclear energy. One of the early female
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