PSS and UVM Work Together for System-Level VerificationIn the early days of the PSS rollout,…Read More
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One of my acquaintances at Intel must have some of the same viewing habits I do, based on a recent Tweet he sent. He was probably watching “The Men Who Built America” on the History Channel and thinking as I have a lot recently about how the captains of industry managed to drive ideas to monopolies in the late 1800s and early 1900s.
… Read MoreDifference
If you take a look at the explosion of the Mobile segment, linked with the fantastic world-wide adoption of smartphone and media tablet, you clearly see that the SC industry evolution during –at least- the next five years will be intimately correlated with the mobile segments. Not really a surprise, but the question I would like … Read More
Calypto announced that Sanjiv Kaul is the new CEO. I first met Sanjiv many years ago when he was still at Synopsys when I interviewed for a position there around the time I transitioned out of Compass and went back to the parent company VLSI. I forget what the position was. Then about three or four years ago when I did some work for Oasys… Read More
Power is a fundamentally hard problem. When you have finished the design, you have accurate power numbers but can’t do anything about them. At the RTL level you have some power information but it is often too late to make major architectural changes (add an offload audio-processor, for example). Early in the design, making… Read More
We’ve been talking about the different technologies for FPGA-based SoC prototyping a lot here in SemiWiki. On the surface, the recent stories all start off pretty much the same: big box, Xilinx Virtex-7, wanna go fast and see more of what’s going on in the design. This is not another one of those stories. I recently sat down with Mick… Read More
In the 1990s, software developers were established users of software configuration management (SCM) tools such as open source RCS/CVS or of commercial systems such as Clearcase. Hardware designers, however, managed design data in ad hoc home-grown ways. ClioSoft’s founder, Srinath Anantharaman, recognized that hardware… Read More
For those of you who follow SemiWiki and the fabless semiconductor ecosystem it has been a very interesting two years:
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Can’t make it to Santa Clara? Join us online!
The detailed 2013 CPTF agenda is now up in preparation for the February 5th event at the Santa Clara Convention Center. This is one of the rare times that you can get a free lunch! Watch this quick video to see what is in store for us this year. Dr. Paul McLellan and I will be there so please… Read More
ASIC design service companies are an essential piece of the SC ecosystem, as well as Silicon Foundries, EDA and IP vendors. Their customers range from pure fabless with no ASIC design resources, who need a third party to turn a concept into a real product (IC) and then market and sale it, to large IDM temporarily lacking design resource… Read More
What is the biggest challenge facing an EDA startup today? By a startup, I mean a brand new company, not a company that already has a few customers and is either on a fast path to success or a slower path whereby the company can continue to grow slowly forever.
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Will 50% of New High Performance Computing (HPC) Chip Designs be Multi-Die in 2025?