800x100 static WP 3

Modern SoC designs require a placement- and routing-aware ECO solution to close timing

Modern SoC designs require a placement- and routing-aware ECO solution to close timing
by Jamie Chen on 05-09-2013 at 9:30 pm

As an applications engineer for over 15 years supporting physical design tools that enable implementation closure, I have seen the complexity of timing closure grow continuously from one process node to the next. At 28nm, the number of scenarios for timing sign-off has increased to the extent that is way beyond the number that … Read More


Are there enough FPGA tools?

Are there enough FPGA tools?
by Luke Miller on 05-09-2013 at 9:00 pm

Sometimes I send my boy to grab me a tool and hours later he comes back with the wrong one. The patient man that I am, I calmly explain what I mean and then the world is right once more. Believe that do ya?

As you know the world is flooded with tools, tools and more tools. We all have our ruts and favorite flows and such but given the huge FPGA … Read More


Places Around the Austin Convention Center

Places Around the Austin Convention Center
by Paul McLellan on 05-09-2013 at 8:05 pm

Jerry Philippe used to work for me at Compass and then very briefly we worked together at VaST. Today he works for Calypto in Austin. And it is the Austin part that is important because Jerry knows where the places are in any city to get good food and drink but Austin is his home.

Austin has an extraordinary number of restaurants and bars.… Read More


Design IP round #2: after road-test, time for the race

Design IP round #2: after road-test, time for the race
by Eric Esteve on 05-09-2013 at 10:58 am

Design IP, at least Interface IP, is about 15 years old, but the market was made of one large provider – Synopsys- with many small vendors around. Chip makers were not very comfortable with this picture, especially the Tier 1 considering that the risk (to see the big one being acquired by one of their direct competitor, say Samsung… Read More


The Morphing of Intel’s Monopoly

The Morphing of Intel’s Monopoly
by Ed McKernan on 05-09-2013 at 12:01 am

It was a generation ago when Intel, less than three years old, created the three fundamental building blocks of the compute era: the DRAM, the EPROM and the Microprocessor, an incredible feat of innovation by any measure. Manufacturing yield, not power or performance determined success of failure and in the first two … Read More


GSA Awards…Nominate!

GSA Awards…Nominate!
by Paul McLellan on 05-08-2013 at 4:50 pm

For 19 years GSA (presumably going back to the days when it was Fabless Semiconductor Association, FSA) has recognized public and private semiconductor companies. The awards are celebrated at a dinner. This year’s dinner is on Thursday December 12th at the Santa Clara Convention Center. The keynote speaker at the dinner… Read More


IP Quality: Foundation of a Successful Ecosystem

IP Quality: Foundation of a Successful Ecosystem
by Eric Esteve on 05-08-2013 at 8:46 am

Talking about Design IP (I mean successful Design IP) lead you to quickly pronounce the two magic key words: Quality and Ecosystem. Those who remember the IP emergence in the mid 90’s know very well why Quality has to be a prerequisite when dealing with Design IP, as they probably have paid the price of mediocre IP quality at that time.… Read More


Improving Design Practices for an Image Sensor IDM

Improving Design Practices for an Image Sensor IDM
by klujan on 05-07-2013 at 8:30 pm

With nearly twenty five years in business, Tanner EDA Application Engineers have seen a wide range of support requests. One consistent topic area is around design data management and design reuse. In one recent instance, our customer, an IDM who produces imaging sensors for infrared vision systems, called on Tanners AE team for… Read More


How To Design a TSMC 20nm Chip with Cadence Tools

How To Design a TSMC 20nm Chip with Cadence Tools
by Paul McLellan on 05-07-2013 at 8:10 pm

Every process node these days has a new “gotcha” that designers need to be aware of. In some ways this has always been the case but the changes used to be gradual. But now each process node has something discontinuously different. At 20nm the big change is double patterning. At 14/16nm it is FinFET.

Rahul Deokar and John… Read More


Bangers: the Best Beer Bar in Austin; Live Oak Brewing, the Best Beer in Austin

Bangers: the Best Beer Bar in Austin; Live Oak Brewing, the Best Beer in Austin
by Paul McLellan on 05-07-2013 at 8:10 pm

OK, enough with all this semiconductor geeky stuff. The important thing about DAC is…where to go to eat to avoid standard issue convention center chicken Caesar salad.

And a 7 minute walk from the convention center is Bangers Sausage House and Beer Gardenwhere you can have the $8 “executive” lunch consisting… Read More