As you can’t have failed to notice by now, 28nm is the last process node that does not require double patterning. At 20nm and below, at least some layers require double patterning. The tightest spacing is typically not the transistors but the local interconnect and, sometimes, metal 1.
In the litho world they call double patterning LELE. This stands for litho-etch-litho-etch which describes the steps taken. Using the first mask, half the polygons are patterned and then etched. Then using the second mask, the other half of the polygons are patterned and then etched. This imposes some restrictions on what can be put on the mask, since it has to be so-called two-colorable, meaning the polygons can be split into two masks such that there each mask has polygons that are sufficiently far apart (there are lots of articles on SemiWiki about the details of this). One problem with LELE is that the second mask is registered onto the first pattern using the fiducial marks (like any other mask) and so there is a level of misalignment that the design must be able to cope with, approximately 10nm, so you can’t actually double the density using double patterning.
So what is beyond double patterning?
- triple patterning called LELELE in the lithography world
- self-aligned double patterning (SADP) also sometimes called sidewall image transfer (SIT)
- EUV, 14nm wavelength instead of 193nm, so we can go back to single exposure
EUV isn’t happening for 10nm unless either there is a miracle in improvement of the power of the light source (and some other problems are solved). Or 10nm slips out several years. Both are possible. The economics of 10nm are somewhere between unknown and dubious.
Triple patterning is pretty much the same as double patterning except that the polygons are partitioned onto three masks. The constraints on the design are different, to ensure this can be done. The big advantage of triple patterning over double is that it is a lot denser. Not three times as dense since the 3 masks will still have some misalignment. In fact because with 3 masks the alignment problems are worse (the distances are tighter) it looks like 3-4nm misalignment is the maximum, which is very hard to achieve.
SADP/SIT removes the potential misalignment between the multiple masks. First a mask is used to put down a temporary sacrificial structure called a mandrel. Then sidewalls are constructed on the sides of the mandrel. The mandrel is removed. This is now double patterning but due to the method of construction there was never a time when a mask was critically aligned on the previous one so the misalignment is removed. Sometimes this is also called pitch doubling since the sidewalls are half the pitch of the mandrels.
This SADP/SIT process can be repeated, using the sidewalls as new mandrels and constructing new sidewalls. This gives self aligned quadruple patterning. With enough process steps (and money) you can get down to 7nm like this without EUV.
One of the biggest decisions in process architecture is to decide what the pitch for various layers should be. The most critical pitch is that for local interconnect and metal 1 since these have major impact on the density of memories and standard cells. Too big a pitch and the process is not competitive since the area is to large. Too tight a pitch and the areas are small but the process is very expensive due to all the extra process steps and masks required. This is why there is so much attention on 14/16nm on what the metal 1 pitch is. An additional complication is that with these two layers it is not possible to live with 1D structures (lay down a grating and then use a cut mask to divide it up) since it is essential to be able to run in both the X and Y directions.
For 10nm it looks like SADP/SIT is needed for a few layers and then double patterning above that. Triple patterning seems like it maybe too expensive to be worth it.