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Triple Patterningby Paul McLellan on 03-19-2014 at 1:00 pmCategories: EDA, Foundries
As you can’t have failed to notice by now, 28nm is the last process node that does not require double patterning. At 20nm and below, at least some layers require double patterning. The tightest spacing is typically not the transistors but the local interconnect and, sometimes, metal 1.
In the litho world they call double patterning… Read More