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Qualcomm JEDEC Mobile Keynote: Memory Bandwidth and Thermal Limits

Qualcomm JEDEC Mobile Keynote: Memory Bandwidth and Thermal Limits
by Paul McLellan on 05-14-2013 at 4:37 pm

I went to some of the JEDEC mobile conference a couple of weeks ago. The opening keynote was by Richard Wietfeld of Qualcomm called The Need for Speed.

He emphasized that smartphones are really setting the pace these days in all things mobile and internet. Over 1/3 of access is on smartphones now. Over 4/5 of searches on smartphones… Read More


Chip and I/O Modeling for System-level Power Noise Analysis and Optimization

Chip and I/O Modeling for System-level Power Noise Analysis and Optimization
by Daniel Payne on 05-14-2013 at 4:13 pm

Cornelia Golovanovworks at LSI Corp in Pennsylvania and is an EMI expert that provides EDA tool and methodology advise to design groups. She earned a PhD in microelectronics and radioelectricity from the Institut national polytechnique de Grenoble, and joined Lucent out of school 12 years ago. We had a chance to talk by phone about… Read More


Jasper Low Power Verification App

Jasper Low Power Verification App
by Paul McLellan on 05-14-2013 at 1:58 am

Today, Jasper announced their new Jasper-Gold Low Power Verification App. This is focused on verifying low power designs with multiple power domains, voltage islands, power shutoff, clock shutoff, and all the other techniques used for reducing power. Of course power is the main driver of SoC design these days, whether it is for… Read More


SOCFIT, Circuit Level Soft Error Analysis

SOCFIT, Circuit Level Soft Error Analysis
by Paul McLellan on 05-13-2013 at 2:50 pm

I blogged recently about reliability testing with high energy neutron beams. This is good for getting basic reliability data but it is not really a useful tool for worrying about reliability while the chip is still being designed and something can be done about it.

That is where IROC Technologies SOCFIT tool comes in. It takes all… Read More


UVM/SystemVerilog: Verification and Debugging

UVM/SystemVerilog: Verification and Debugging
by Daniel Payne on 05-13-2013 at 2:45 pm

At DAC in just three weeks you can learn about which EDA vendors are supporting the latest UVM 1.1d (Universal Verification Methodology) standard as defined by Accellera. One of those EDA vendors is Aldec, and they have a 45 minute technical session that you can register for online. Space will fill up quickly, so get signed up sooner… Read More


Sonics-ARM Form A Potent IP Combination

Sonics-ARM Form A Potent IP Combination
by Randy Smith on 05-13-2013 at 1:30 pm

Recently, Sonics and ARM entered into an agreement whereby ARM licensed a significant portion of Sonics’ patent portfolio. Sonics, Inc. is one of the leading providers of connectivity IP often referred to as network-on-chip, or NoC. ARM is the leading provider of processor intellectual property (IP). The potential scope… Read More


A random walk down OS-VVM

A random walk down OS-VVM
by Don Dingee on 05-13-2013 at 11:14 am

Unlike one prevailing theory of financial markets, digital designs definitely don’t function or evolve randomly. But many engineers have bought into the theory that designs can be completely tested randomly. Certainly there is value to randomness, exercising all combinations of inputs, including unexpected ones a designer… Read More


Tektronix at #50DAC

Tektronix at #50DAC
by Daniel Nenni on 05-13-2013 at 10:00 am

If we grew up in similar eras you will know Tektronix as a company that manufactures test and measurement devices. Every lab I was in during high school and college had Tek oscilloscopes and logic analyzers. At #50DAC however, attendees that visit Tektronix will experience firsthand RTL simulation-level visibility to multi-FPGA… Read More


Cliosoft CEO on Design Collaboration Challenges!

Cliosoft CEO on Design Collaboration Challenges!
by Daniel Nenni on 05-12-2013 at 8:30 pm

Cliosoft was one of the first SemiWiki subscribers and it is a pleasure to work with them. They have one of the busiest landing pages with more than 30 articles authored by Daniel Payne, Paul McLellan, and myself. Srinath and I have lunch occasionally and exchange ideas, observations, and experiences:

Q: What are the specific designRead More


A Big Boost for Equivalency Checking

A Big Boost for Equivalency Checking
by Daniel Payne on 05-12-2013 at 1:41 pm

Thirty years ago in 1983 Professor Daniel Gajski and Kuhn created the now famous Y-Chart to show the various levels of abstraction in electronic system design:

We can still use this Y-Chart today because it still pertains to how engineers are doing their SoC designs. Along the Behavioral axis there is a need to know that each level… Read More