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On-Chip Clock Generation beyond Phase Locked Loop

On-Chip Clock Generation beyond Phase Locked Loop
by Daniel Nenni on 03-07-2014 at 8:00 am

Inside a today’s typical VLSI system, there are millions of electrical signals. They make the system perform what it is designed to do. Among those, the most important one is the clock signal. From an operational perspective, clock is the timekeeper of the electrical world inside the chip/system. From a structural perspective, clock generator is the heart of the chip; clock signal is the blood; and clock distribution network is the vessel.

Timekeeper has played and is playing a critical role in our human life. History shows that the progressive advancement of our civilization is only made possible by the steady refinement of the timekeeper: the clock/watch. The same is true for VLSI system. The purpose of VLSI system is for processing information. The efficiency of performing this task is highly dependent on the time scale used. This time scale is controlled by the clock signal. It has two key aspects: its size (the absolute clock frequency) and its resolution (the capability of differentiating nearby frequencies, or the frequency and time granularity). In addition, another characteristic is also important: the speed that time scale can be switched from one to another (the speed of clock frequency switching). Phase Locked Loop (PLL) has traditionally been used as on-chip generator of clock signal. It is a beautiful blend of digital and analog circuits in one piece of hardware. From a reference time scale, it can generate other time scales. However, due to its usage of compare-then-correct feedback mechanism, the choice of time scales that can be produced is limited. Equally harsh is the problem that the change of time scale (frequency switching in PLL) takes very long time. Although PLL has played a key role that makes today’s VLSI system magnificent, these two problems are limiting chip architect’s capability for creating further innovation.

The source of the problem originates from the very fact that electrical circuit is not born for handling time, but magnitude (or level). Inside a circuit, information is represented by the medium of electron. It is created on the magnitude of electron flow, using proportional (analog) or binary (digital) relationships. Time is created indirectly through a voltage level crossing a predetermined threshold. Therefore, the task of building a timekeeper inside VLSI system is inherently difficult since it relates two basic properties of the universe: time and force. In implementation, another fact has made the task of creating time inside circuit even more challenging:since the first day that clock signal is introduced into VLSI design, it is assumed that all the pulses inside a particular clock pulse train have to be equal-in-length. This presupposition has limited our options in the creation of timekeeper circuit. Consequently, our current solution is not completely satisfactory: 1) we cannot generate any arbitrary frequency we want. 2) we cannot switch frequency quickly.

Since timekeeper controls VLSI system’s operation pace through clock-driving-circuit, a fundamental question can be asked: do all the pulses in a clock pulse train have to be equal-in-length? This question is equivalent to asking: what does clock frequency really mean? In 2008 a novel concept, Time-Average-Frequency, is introduced. It removes the constraint that all pulses (or clock cycles) must be equal-in-length. It is based on the understanding that clock frequency is used to indicate the number of operations executed (or events happened) within the time window of one second. As long as the specified number of operations is completed successfully in a specified time window (such as one billion operations within one second for a 1 GHz CPU), the system does not care how each operation is carried out in detail. This breakthrough in clock frequency concept is crucial. It can free our hand in making the clockwork.

Figure Clock as a technology.

From the day of Robert Noyce and Jack Kirby’s first integrated circuit in 1959 to today’s system of billions-transistors-on-a-chip, the art of integrated circuit design can be roughly individualized into three key areas: processor technology, memory technology and analog technology. Processor technology focuses its attention on how to build efficient circuit to process information. Using transistors to do logic and arithmetic operation with high efficiency is at its highest priority. Memory technology is the study of storing information in circuit. Its aim is to store and retrieve information in large amount and in high speed. Analog technology squares its effort at circuit of interfacing electrical system with human. Inside VLSI system, information is processed in binary fashion. Once outside, information is used by us in proportional style since our five senses is built upon proportional relationship. Analog circuit is the bridge in between. During the past several decades, the advancements in these three circuit technologies have made today’s VLSI system very powerful. However the driver of these three technologies, the clock, has not seen fundamental amelioration. The time scale is not flexible: the available clock frequencies are limited; the switching between frequencies is slow.

To improve VLSI system’s information-processing-efficiency further, the next opportunity is at the method of clocking: 1) we need a flexible on-chip clock source; 2) and it needs to be available to chip designer at a reasonable cost. Now is the time for clock being recognized as a technology, as illustrated in above figure. In this field, there are four key issues: high-clock-frequency, low-noise, arbitrary-frequency-generation and fast-switching. The first two have been studied intensively by researchers. The last two have not drawn much attention. There are two reasons. The first one is that arbitrary-frequency-generation and fast-frequency-switching are difficult to achieve, especially to achieve them simultaneously (in contrast, arbitrary-voltage-generation and fast-voltage-switching are easy to do). The second reason is that chip/system architect has not asked for it. As a result, circuit designer does not have the motivation. These two factors are cause-and-effect of each other: system architect does not know that it can be done; circuit designer does not know that it is needed. The goal of this article is to break this lock, to provide a vision that it can be done and it is useful. The aim of Time-Average-Frequency is to provide the means of making flexible on-chip clock source available to chip designer. This concept and technology is a link between circuit and system: a circuit level enabler for system level innovation.

This book “Nanometer Frequency Synthesis beyond Phase Looked Loop” introduces a new way of thinking about the fundamental concept of clock frequency. It presents a new circuit architecture for frequency synthesis: Time-Average-Frequency based Direct Period Synthesis. It proposes a new circuit component: Digital-to-Frequency Converter (DFC). Its influence can go beyond clock signal generation. It is a new frontier for electronic system design.

Nanometer Frequency Synthesis Beyond the Phase-Locked Loop (IEEE Press Series on Microelectronic Systems) by Liming Xiu

lang: en_US

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