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DAC 2013 Pavilion Panel: Affiliation Avenue – The Road to Success!

DAC 2013 Pavilion Panel: Affiliation Avenue – The Road to Success!
by Holly Stump on 05-06-2013 at 7:00 pm

Join us for a free career-building panel at DAC 2013, sponsored by Women in Electronic Design.
· Don’t go it alone! How many times have you heard it?


A lively panel of luminaries discuss how alliances are critical to our success, and cover networking and negotiating skills for achieving personal satisfaction and professional visibility.
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Atrenta at DAC…SpyGlass is Everywhere

Atrenta at DAC…SpyGlass is Everywhere
by Paul McLellan on 05-06-2013 at 6:43 pm

Atrenta are at booth 1847 in the exhibit hall where there will be regular presentations in the “RTL Signoff Theater” and lots of presentations on various aspects of SpyGlass, GenSys and BugScope in their suites. The registration page for the suite sessions is here. Just who is presenting in the RTL Signoff Theater … Read More


More Injustice in EDA Lawsuits

More Injustice in EDA Lawsuits
by Daniel Payne on 05-06-2013 at 6:38 pm

ss ipad

There’s a one-person EDA start-up called iSchematics.com that offers schematic capture and cloud-based simulation for both web browsers and mobile devices like the iPhone and iPad that is being sued. I’ve blogged about their EDA tools before:

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Mobile Storage Interfaces: There are a Lot

Mobile Storage Interfaces: There are a Lot
by Paul McLellan on 05-06-2013 at 5:39 pm

Storage interfaces for mobile are evolving rapidly, in particular with the Universal Flash Storage (UFS) standard. So how do you test a design? If you want to test a design that accesses, say, an SD card then you can wander into Fry’s and buy an SD card for a few dollars. But to design an interface to UFS is a bit harder since the … Read More


How to Blast Your Chip with High Energy Neutron Beams

How to Blast Your Chip with High Energy Neutron Beams
by Paul McLellan on 05-06-2013 at 3:49 pm

So you want to know how reliable your chips are and how susceptible they are to single event effects (SEEs) where a neutron or an alpha particle causes a storage element (flop or memory cell) to flip in a way that alters the behavior of the device. There are two ways a particle hitting a device might not cause a problem. Firstly, the particle… Read More


Which is the best FPGA – Xilinx

Which is the best FPGA – Xilinx
by Luke Miller on 05-06-2013 at 10:00 am

Your corporate training will teach you there is no such thing as stereo types and they are bad, naughty. We all know they are true; it’s just some companies now of days try to force the worker bees to do a flash erase and drop your brain at the door. I never participated in that and as you can imagine it went very well. Dilbert is true…

I am … Read More


Customer Stories at DAC#50

Customer Stories at DAC#50
by Daniel Nenni on 05-05-2013 at 8:10 pm

When you think Apache Design you probably think Low Power Design and what stuffed animal will they give away at DAC. The other thing you should think about is how the top semiconductor companies around the world use Apache products for leading edge semiconductor design. Demos are fine, but there is nothing like talking directly … Read More


A Tale of Two Events, Make that Three, Wait…How about Four?

A Tale of Two Events, Make that Three, Wait…How about Four?
by Camille Kokozaki on 05-05-2013 at 8:05 pm

It is increasingly apparent that Kurzweil’s Singularity is sure getting near, if it is not here already 32 years too soon. Not a week goes by without missing or needing to attend a key conference, seminar, symposium, summit, with each having parallel streams, panels, exhibits, demos, social networking. Not only are we informed,… Read More


Analog IC Verification – A Different Approach

Analog IC Verification – A Different Approach
by Daniel Payne on 05-04-2013 at 5:33 pm

Analog design seems to suffer from a huge gap when it comes to testing and verification. While some of this gap is natural – after all, often the only way to verify whether a particular design is working is to look at actual simulation waveforms – it still seems like a lot can be done to bring process into this sphere of the… Read More


Solido CEO on 20nm/16nm TSMC and GLOBALFOUNDRIES Design Challenges

Solido CEO on 20nm/16nm TSMC and GLOBALFOUNDRIES Design Challenges
by Daniel Nenni on 05-04-2013 at 11:00 am

EDA needs more CEOs like Amit Gupta. Solido, which is now profitable, is his second AMS EDA company. The first, Analog Design Automation (ADA), was purchased by Synopsys for a hefty multiplier. Prior to becoming an EDA entrepreneur, Amit was product manager for the wireless group at Nortel and a hardware engineer for the RF communications… Read More