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ISSCC 2014 SerDes Presentation

ISSCC 2014 SerDes Presentation
by Daniel Nenni on 03-18-2014 at 9:00 pm

For those of you who missed the IEEE International Solid-State Circuits Conference last month some of the presentations are now hitting the company websites. The theme of this year’s conference was SILICON SYSTEMS BRIDGING THE CLOUD:

Traditional computing solutions tend to be very vertically oriented. The cloud brings the promise of many benefits such as flexible computing power, shared software applications, and centralized databases. Solutions for bridging the gaps in the cloud will need to evolve from the technologies and systems we have today. New approaches to sharing networks, infrastructure and data storage will be required, as will new approaches to securing these shared resources. These solutions will challenge systems designers to consider new system architectures and will also require advances in circuit and technology.ISSCC2014is looking for novel system and circuit solutions to create a truly connected world.

Several of the companies I work with presented or were part of the research that a presentation was based on. Here is the first and last paragraph of a paper featuring work done by Kandou Bus:

A Pin and Power Efficient Low Latency 8-12Gb/s/wire 8b8w-Coded SerDes Link for High Loss Channels in 40nm Technology

The continuing demand for higher bandwidth in serial interconnects has pushed the symbol rate of differential lanes into the high insertion loss region of channels. Multi-level signaling such as differential PAM-4 [1] has been used to mitigate the loss of electrical channels by lowering the signal spectrum. Such an approach suffers from lower SNR tolerance as well as higher susceptibility to crosstalk and ISI as compared to differential signaling (DS).


The 8b8w-coded SerDes link has been fabricated on a 40nm 10LM process, Figure 26.3.7. The design includes an option to operate in legacy quad-lane DS mode. The test chip can be controlled with SPI and includes data generators (PRBS31, PRBS9 and custom patterns), error counters and other test features like eye-scope and analog test bus. The test setup is shown in Figure 26.3.5 and utilizes multiple 2.4mm connectors, cables and board traces. The link achieves power efficiency of <4.3 pJ/bit at 12 Gb/s/wire. Bathtub measurements were taken over multiple channel configurations and BER <8e-15 was achieved at 12 Gb/s/wire with PRBS31 data over channels with 15dB loss. Common-mode, power supply and crosstalk noise tests do not show any significant degradation in BER. Per-wire de-skew capability of up to 1-UI was demonstrated by running the link on channels with mismatched cables. Measurements show a 2x improvement in power efficiency when compared with DS-mode at the same throughput.

Session paper and slides

About Kandou Bus S.A.

Headquartered in Lausanne, Switzerland and founded in 2011, Kandou Bus is an innovative interface technology company specializing in the invention, design, license and implementation of unmatched chip-to-chip link solutions. Kandou’s Chord™ technology lowers power consumption and improves overall performance of semiconductors, unlocking new capabilities in electronic devices and systems. www.kandou.com.

More Articles by Daniel Nenni…..

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