CEO Interview with Dr. Naveen Verma of EnCharge AINaveen Verma, Ph.D., is the CEO and Co-founder…Read More
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WEBINAR Unpacking System Performance: Supercharge Your Systems with Lossless Compression IPsIn today's data-driven systems—from cloud storage and AI…Read More
Thanks to memory controller expert Marc Greenberg, Marketing Director for DDRn Controller IP with Synopsys, for this post “Qualcomm announces first application processor with LPDDR4 capability”. According with Marc, this Application Processor, the Snapdragon 810, is “the first product that I’m aware of that will use LPDDR4… Read More
Learning an HDL language or an HDL simulator are two different things, so I wanted to see what was available for learning a vendor-specific HDL simulator. I’ve already taught Verilog as an instructor using both ModelSim and Active-HDL simulators, however we only used a handful of commands in the class and labs in order to … Read More
Pop quiz: eSilicon has a big IP development group in what Asian country? If you didn’t know and you guessed, you probably got it wrong with China or India. It is Vietnam. In fact they have two sites. One in Ho Chi Minh City (that used to be called Saigon) and one in Da Nang.
At Electronic Design Process Symposium (EDPS) held last … Read More
“Failure to plan is planning to fail.” If that is true – and it has been quoted verbatim or slightly modified so many times throughout modern history, there has to be some truth – why does most of the engineering community seem to detest planning so much?
Engineering planning doesn’t mean whipping out a block diagram or pseudo code,… Read More
We have had the Snowden revelations that the NSA has gone rogue, Target lost a zillion credit cards, the Heartbleed bug meaning that main security protocol of the internet had been coded up wrong for a couple of years, theft of records from RSA and more. One result is that people do not completely trust a security system that depends… Read More
In an era of SoCs with millions of gates, hundreds of IPs and multiple ways to verify designs through several stages of transformations at different levels of hierarchies, it is increasingly difficult to handle such large data in a consistent and efficient way. The hardware and software, and their interactions, have to be consistent… Read More
In a complex world of SoCs with multi-million gates and IPs from several heterogeneous sources, verification of a complete semiconductor design has become extremely difficult, and it’s not enough. In order to ascertain the right intent of the design throughout the design cycle, debugging at various stages of the design cycle… Read More
Cadence announced today that it is acquiring Jasper Design Automation for $170M in an all-cash offer. Jasper has $24M in cash so it is really an acquisition for around $145M. i think that is around 4X revenue but I only know rumors about Jasper’s revenue numbers.
All the big 3 already have their own formal technology but the … Read More
Pop quiz: Name one of the hottest applications for non-volatile memory – A) processor and code configuration; B) RFID tags; C) secure encryption keys; D) all the above. The answer is D, but not in the way you may be thinking; a new approach is using all these ideas at once, combined in SoC designs targeting advanced security … Read More
I went to a briefing last Tuesday where Samsung and GlobalFoundries announced that they have the same process at 14nm. Dan already wrote about itso it is old news in one sense. But I really think people underestimate its importance. In essence, reading between the lines, Samsung is licensing GF their 14nm process. This is driven … Read More
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