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SoCs More Vulnerable to ESD at Lower Nodes

SoCs More Vulnerable to ESD at Lower Nodes
by Pawan Fangaria on 03-11-2015 at 1:00 pm

Electro Static Discharge (ESD) has been a major cause of failures in electronic devices. As the electronic devices have moved towards high density SoCs accommodating ever increasing number of gates at lower process nodes, their vulnerability to ESD effects has only increased. Among the reasons for ESD failures in SoCs, device… Read More


Innovus: Cadence’s Next Generation Implementation System

Innovus: Cadence’s Next Generation Implementation System
by Paul McLellan on 03-11-2015 at 7:00 am

Yesterday was the first day of CDNLive. There were three keynotes. The first was by Lip-Bu Tan, Cadence’s CEO (and the Chairman of Walden International that he will be the first to remind you). The most interesting tidbit was that Cadence now has over 1000 people working on IP and that it represents 11% of their revenue. Then… Read More


On-Chip Power Integrity Analysis Moves to the Package

On-Chip Power Integrity Analysis Moves to the Package
by Tom Simon on 03-11-2015 at 1:00 am

Power regimes for contemporary SOC’s now include a large number of voltage domains. Rail voltages are matched closely to the performance and power requirements of various portions of the design. Indeed, some of the supply voltages are so low that the noise margins in these domains is exceedingly low. Higher voltage domains are… Read More


Altera 14nm and 10nm Update!

Altera 14nm and 10nm Update!
by Daniel Nenni on 03-10-2015 at 7:00 pm

In preparation for this blog I Googled around to get the latest information made available by Altera to see if it matches up with what I know from discussions amongst the fabless semiconductor ecosystem companies. Unfortunately when I Googled Altera+20nm+14nm the first three entries from the Altera website were Error 404 PageRead More


FinFET Design Enablement

FinFET Design Enablement
by Daniel Payne on 03-10-2015 at 1:00 pm

We read about FinFET technology in the semiconductor press daily now, thanks to Intel introducing their TriGate transistors starting in 2011 and creating a race with foundries and IDMs to switch from planar CMOS nodes. To get some perspective about the progress of FinFET IP and EDA tools I spoke with two experts from Synopsys, Swami… Read More


2015, the Year of the Sheep…And the 16nm FPGA

2015, the Year of the Sheep…And the 16nm FPGA
by Paul McLellan on 03-10-2015 at 7:00 am

If you live in California anyway, with its large Asian population, you can’t have helped noticing that it was the Lunar New Year a couple of weeks ago, the start of the year of the sheep. A couple of days after the New Year, Xilinx announced their new families of what they now call FPGAs, 3D ICs and MPSoCs. But which the rest of us … Read More


Why did Mentor Acquire Tanner EDA?

Why did Mentor Acquire Tanner EDA?
by Daniel Nenni on 03-09-2015 at 11:30 pm

You have to love when a professional journalist leaks a story and cites a “source close to the acquisition.” News flash: Anyone “close” to the acquisition is under NDA which is a legally binding agreement, not very professional if you ask me. Bloggers however can write whatever they want but since I was actually “close” to … Read More


MIPI Ecosystem talk at Seattle this week

MIPI Ecosystem talk at Seattle this week
by Eric Esteve on 03-09-2015 at 7:02 pm

Sunday 8, March 2015. D-day minus one before the MIPI Alliance Face to Face meeting, starting in Seattle on Monday 9[SUP]th[/SUP] for five days. MIPI members are joining from all around the world to attend this one week meeting. If you take a look at www.mipi.org you will see the names of the 263 members from MIPI. A strong ecosystem… Read More


Apple Watch Announcement

Apple Watch Announcement
by Daniel Payne on 03-09-2015 at 1:00 pm

Rock music, invitation only tickets, hollywood lighting, journalists from around the world, live streaming on the web, yes, another typical Apple-orchestrated product launch on Monday, March 9th at the Yerba Buena Center in California.

Up first was a video about Apple’s store opening in West Lake China with superb cinematography.… Read More


Voltage Limbo Dancing: How Low Can You Go?

Voltage Limbo Dancing: How Low Can You Go?
by Paul McLellan on 03-09-2015 at 7:00 am

All chips these days have to worry about power. Indeed it is typically the top of the priority list of concerns, above performance and even area. Transistors are effectively fast and free, but you can’t have too many of them (at least turned on at once). The most obvious way to reduce power is to lower the supply voltage. This … Read More