BannerforSemiWiki 800x100 (2)

Assertion IP (AIP) for Improved Design Verification

Assertion IP (AIP) for Improved Design Verification
by Daniel Payne on 10-14-2025 at 10:00 am

Detailed flow min

Over the years design reuse methodology created a market for Semiconductor IP (SIP), now with formal techniques there’s a need for Assertion IP (AIP). Where each AIP is a reusable and configurable verification component used in hardware design to detect protocol and functional violations in a Design Under Test (DUT).  LUBIS … Read More


Secure-IC and Silicon Labs Raise the Bar for Hardware Security

Secure-IC and Silicon Labs Raise the Bar for Hardware Security
by Mike Gianfagna on 10-14-2025 at 8:00 am

Secure IC and Silicon Labs Raise the Bar for Hardware Security

Cybersecurity is getting more critical every day. Thanks to sophisticated AI attacks, the need for hardware chip-level security is greater than ever. To fortify hardware against these types of attacks is not easy. There are three key attributes of a successful strategy: a well-designed root-of-trust, collaboration to ensure… Read More


Why Choose PCIe 5.0 for Power, Performance and Bandwidth at the Edge?

Why Choose PCIe 5.0 for Power, Performance and Bandwidth at the Edge?
by Kalar Rajendiran on 10-14-2025 at 6:00 am

PCIe 5.0 Impact Across Markets

Synopsys recently held a webinar session on this topic and Gustavo Pimentel, Principal Product Marketing Manager at the company led the webinar session. Going into the webinar session, I found myself wondering: why focus on PCIe 5.0, eight years after its release? With the industry buzzing about Edge AI, cloud computing, and … Read More


Protect against ESD by ensuring latch-up guard rings

Protect against ESD by ensuring latch-up guard rings
by Admin on 10-13-2025 at 10:00 am

fig1 latchup event

By Mark Tawfik

Overview: Protecting ICs from costly ESD and latch-up failures

Electrostatic discharge (ESD) events cost the semiconductor industry an estimated $8 billion annually in lost productivity, warranty claims and product failures [1].

Ensuring the robust protection of integrated circuits (ICs) against various… Read More


The 2025 Semi Industry Forum: On the Road to a $1 Trillion Industry

The 2025 Semi Industry Forum: On the Road to a $1 Trillion Industry
by Daniel Nenni on 10-13-2025 at 6:00 am

image (1)

The global semiconductor industry stands at a defining moment in its history. Having surpassed $600 billion in annual revenue, the path to a $1 trillion market is no longer a distant dream but an achievable milestone within the next decade. The annual 2025 Semi Industry Forum, organized by Silicon Catalyst, brings together the… Read More


Selling the Forges of the Future: U.S. Report Exposes China’s Reliance on Western Chip Tools

Selling the Forges of the Future: U.S. Report Exposes China’s Reliance on Western Chip Tools
by Daniel Nenni on 10-12-2025 at 10:00 am

Employees are seen working on the final assembly of ASML's TWINSCAN NXE:3400B semiconductor lithography tool with its panels removed, in Veldhoven

The U.S. House Select Committee on the Strategic Competition Between the United States and the Chinese Communist Party released a bombshell report titled “Selling the Forges of the Future” on October 7, 2025, detailing how the People’s Republic of China is stockpiling semiconductor manufacturing equipment… Read More


SEMICON West AZ- Congress & China- Memory Madness- AI Semiconductor Tsunami

SEMICON West AZ- Congress & China- Memory Madness- AI Semiconductor Tsunami
by Robert Maire on 10-12-2025 at 8:00 am

Semicon West Phoenix 2025

– First SEMICON in Arizona was great- should make it permanent
– Congress finally wakes up to China issues long after cows are gone
– Memory cycle in support of AI could be huge but scary at same time
– AI demand seems bottomless- but may distort chip industry dynamics

Phoenix SEMICON was wonderful!

The crowds… Read More


Podcast EP310: On Overview of the Upcoming DVCon Europe Conference and Exhibition with Dr. Mark Burton

Podcast EP310: On Overview of the Upcoming DVCon Europe Conference and Exhibition with Dr. Mark Burton
by Daniel Nenni on 10-10-2025 at 10:00 am

Daniel is joined by Dr. Mark Burton, the General Chair for this year’s DVCon Europe. DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits.

Mark shares his long history of involvement in DVCon with Dan. He … Read More


Exploring TSMC’s OIP Ecosystem Benefits

Exploring TSMC’s OIP Ecosystem Benefits
by Daniel Nenni on 10-10-2025 at 6:00 am

TSMC Booth

Now that the dust has settled let’s talk more about TSMC’s Open Innovation Platform. Launched in 2008, OIP represents a groundbreaking collaborative model in the semiconductor industry. Unlike IDMs that controlled the entire supply chain, OIP fosters an “open horizontal” ecosystem uniting TSMC… Read More


Demand Meets Design: RISC-V and the Next Wave of AI Hardware

Demand Meets Design: RISC-V and the Next Wave of AI Hardware
by Kalar Rajendiran on 10-09-2025 at 10:00 am

Optimum Compute Watt Per Layer

Artificial intelligence (AI) is transforming every layer of computing, from hyperscale data centers training trillion-parameter models to battery-powered edge devices performing real-time inference. Hardware requirements are escalating on every front: compute density is increasing, power budgets are tightening, … Read More