A couple of days ago Intel announced a collaboration with eASIC. Here is the opening paragraph of the press release:Intel Corporation today announced plans to develop integrated products with eASIC Corporation that combine processing performance and customizable hardware to meet the increasing demand for custom compute … Read More




Samsung Foundry Update!
It is hard to believe that Samsung is celebrating their 10[SUP]th[/SUP] anniversary in the foundry business this year. It certainly has not been an easy road but as of late you cannot argue with the results. Samsung is the first foundry to put 14nm silicon into smart phones, beating the #1 semiconductor company (Intel) and the #1 … Read More
Quark Adds Muscle to Intel in the IoT World
We have been hearing about Intel’s Quark processor, which is based on its good old Pentium, making waves in IoT world. The CPU core of Quark is said to be the smallest in Intel. It is supposed to be inexpensive and extremely low in power; a perfect combination for IoT devices. The Pentium architecture equips the processor to perform… Read More
"An art can only be learned in the workshop of those who are winning their bread by it"
That was said by the novelist Samuel Butler, but it is not a bad description of why you should spend the Sunday at DAC in one of the workshops that are taking place that day.
One workshop is on Design Automation for Beyond CMOS Technologies. Before getting to design automation, it is good to start with which technologies are potentially… Read More
Chip Design – Coming of Age in the Computer Age
Previously, I examined chip design in the late 1970s and early 1980s. It was a nostalgic ride – thanks to all those who shared their stories. I enjoyed reading all of them. I drew two basic conclusions in the prior post:
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Saving Time and Money on Your Next SoC Project
Every SoC project that I know of wants to finish on time, under budget, and maximize profits per device. When I first started out doing DRAM design I learned that we could maximize profit by doing shrinks of existing designs, move from ceramic to plastic packages, and reduce the amount of time spent on a tester. Today, the economic … Read More
Beware of Parameter Variability in Clock Domain Crossings
How should we assess the risk of harmful metastability in a clock domain crossing (CDC) when the semiconductor process has significant parameter variability? One possibility is to determine the MTBF of a synchronizer at the worst-case corner of the CDC. But that approach has some conflicting complications:
- Synchronizer failures
ARM A57 (A53) Virtualizer + IP Accelerated = ?
Hybrid IP Prototyping Kit from Synopsys!
Synopsys has launched IP Accelerated initiative last year. The goal was clearly to accelerate Time-To-Market by providing a complete set of “tools” to augment design productivity:
- IP Prototyping Kit with reference designs work out-of-the-box
- IP software development kits enable early
Is Low Power a Challenge? ICE-Grain Answers the Challenge
Blogs have limited wordcount so insert your own generic opening paragraph here about the importance of low power in IC design. Mention IoT and cloud datacenters for extra credit.
It is well-known that the biggest reductions in power come from changes at the architectural level. Tools and process can do some things and since they… Read More
Experts Talk at Mentor Booth
It’s less than four weeks to go at DAC 2015 and the program is final now. So I started investigating new technologies, trends, methodologies, and tools that will be unveiled and discussed in this DAC. In the hindsight of the semiconductor industry over the last year, I see 14nm technologies in the realization stage and 10nm beckoning… Read More
Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot