CEO Interview: Khaled Maalej, VSORA Founder and CEOKhaled Maalej is founder and CEO of VSORA,…Read More
Soitec Delivers the Foundation for Next-Generation InterconnectsSoitec is a unique company that is at…Read More
Electrical Rule Checking and Exhaustive Classification of ErrorsThe goal of SoC design teams is to…Read More
Early SoC Dynamic Power Analysis Needs Hardware EmulationThe relentless pursuit for maximizing performance in semiconductor…Read More
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The world of IPs in the semiconductor landscape has completely changed the semiconductor design scenario, specifically the fabless design space. Today IPs are key components of any large semiconductor design, in the same way as auto ancillaries in auto design. It’s just the beginning, in the days to come we will see SoCs just as… Read More
Everyone in EDA is really smart. People who leave EDA and go and work in other industries, especially people who left in the late 1990s for internet startups, notice that this is not true elsewhere. Not that there aren’t smart people in internet startups, just that not everyone is. EDA is an industry where you need a master’s… Read More
The IoT (Internet of Things) creates an ambivalence within me. Part of me hates computers and being connected, the other is currently working on a boiler controller that even adaptively predicts and senses when the next wood load is needed and alerts the wife. Yup pray for her. I really use FPGAs and CPLDs around the farm and I am slowly… Read More
Usually, we get the incremental story in news: this new release is x percent better at this or that than the previous release, and so on. Often missing is the big picture, telling how the pieces all tie together. Synopsys took on that challenge in their latest FPGA-based prototyping webinar. … Read More
Last week was ARM’s quarterly earnings call. Simon Segars, the CEO, and Tim Score, the CFO, presented from London.
First, the numbers:
Once upon a time there was a struggle for verification completion of semiconductor designs at gate level. Today, beyond imagination, there is a struggle to verify a design with billions of gates at the RTL level which may never complete. The designs are large SoCs with complex architectures and several constraints of area, performance,… Read More
There has been a lot of controversy about whether FD-SOI is or is not cheaper to manufacture than FinFET. Since right now FinFET is a 16nm process (22nm for Intel) and FD-SOI is, for now, a 28nm process it is not entirely clear how useful a comparison this is. Scotten Jones has very detailed process cost modeling software (that is what… Read More
Royalty is a critical component in any IP deal. SoC companies want IP companies to share the risk of success (or failure) of their SoC and to enable that they want IP vendors to accept a substantial part of their payment to be paid as royalty. But the customers are also not very interested to shell out huge money to IP companies if the SoC… Read More
One of the things I do in my spare time is listen to quarterly conference calls and try to sort fact from fiction. I compare past calls to the current one and attempt to predict what’s coming next. Confucius said, “Study the past if you would define the future” and I’m a big believer in that.
Paul McLellan wrote about the Xilinx call earlier… Read More
On Thursday, July 31[SUP]st[/SUP] at 8 AM Pacific Daylight Time I’ll be moderating a webinar that will demo eSilicon’s new GDSII quoting portal. You can find more details about the webinar here, and you can register here.
I’ve worked with a lot of companies that do advanced custom IC designs. Getting a quote that covers all the NRE… Read More
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Real men have fabs!