So what comes after FinFETs? At 14/16nm (or 22nm if you are Intel) we had FinFET transistors, where the channel was no longer planar but stuck out of the wafer vertically, and the gate wrapped around it on 3 sides. The key thing that made FinFET transistors attractive was that the channel was thin so that the gate controlled it well. … Read More
Siemens EDA Makes 3D IC Design More Accessible with Early Package Assembly Verification2.5D and 3D ICs present special challenges since…Read More
Webinar: Fine-grained Memory Protection to Prevent RISC-V Cyber AttacksMost organizations are aware of cybercrime attempts such…Read More
Webinar: Samtec and Achronix Expand AI in the Data CenterThe performance demands of data centers continue to…Read More
Don't Settle for Less Than Optimal - Get the Perfect Inductor Every TimeThe meaning of the word “Veloce” is “blazing…Read More
Synopsys is Paving the Way for Success with 112G SerDes and BeyondData communication speeds continue to grow. New encoding…Read More
IoT Application: Road Biking Fitness
Eleven months ago I started a fitness kick in order to lose some weight, get healthy and have more energy, so I picked a familiar activity, road cycling. Being an engineer I have always loved measuring things, like my speed and distance, however I had an old-fashioned cyclocomputer called the Cateye Velo 2. This device connected … Read More
Semiconductor Revenue Trends
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Nescire autem quid ante quam natus sis acciderit, id est semper esse puerum. (Not to know what happened before you were born is to remain forever a child.)–Cicero
2014 is destined to be a pivotal year for Silicon Valley and High Tech in general. End user markets have been stagnating or declining over the last… Read More
Analog Model Equivalence Checking Accelerates SoC Verification
In the race to reduce verification time for ever growing sizes of SoCs, various techniques are being adopted at different levels in the design chain, functional verification being of utmost priority. In an analog-digital mixed design, which is the case with most of the SoCs, the Spice simulation of analog components is the limiting… Read More
Speeding up IP and Data Management
IP and Data Management (DM) for SoC teams has gradually moved from ad-hoc approaches using simple Excel spreadsheets, to home-grown software that is specific to a project or company, and finally to commercially supported tools. One such commercial toolset for IP lifecycle management is from Methodics, named ProjectIC –… Read More
Should we pay the price of Innovation?
I agree that this question sounds stupid: nobody is forcing me to buy an innovative product, or even a gadget, if I don’t want to pay a high price, I just don’t buy the product. But it seems that some people don’t really think that way. The story is related to Qualcomm sales in China, and recently announced partnership with SMIC…
The Partnership… Read More
IBM thinks neural nets in chip with 4K cores
Neural networks have been the darlings of researchers since the 1940s, but have eluded practical hardware implementations on all but a small scale, or an enormous one given how many processing elements and interconnects are needed. To make significant brain-like decisions, one needs at least several thousand fairly capable… Read More
Layout-aware Diagnosis
Traditional test methodologies have been based on the functional model, that is to say the netlist. The most well-known is probably the stuck-at model which grades a sequence of test vectors by whether they would have managed to notice the difference between a fully functional design and one where one of the signals was permanently… Read More
Who will Manufacture Apple’s Next SoC?
Just to review: The brain inside the current Apple iPhone 5s is the A7 SoC manufactured by Samsung using a 28nm process. The A6 (iPhone 5) and A5 (iPhone 4s) are based on Samsung 32nm. The rest of the Apple SoCs also used Samsung processes. I think we can all now agree that the coming Apple A8 SoC (iPhone 6) will use the TSMC 20nm process.… Read More
Hybrid Memory Cube and the Intel Knights Landing
While looking for information on a Xilinx Spartan 6 Project with DDR memory I came across a new type of DRAM called the Hybrid Memory Cube (HMC). The technology made me want to take a closer look:
The Hybrid Memory Cube is like a stack of DDR chips stacked die on die using through silicon vias to interconnect the dies the bottom die in not… Read More
Application-Specific Lithography: Sense Amplifier and Sub-Wordline Driver Metal Patterning in DRAM