The Death of Moore’s Law

The Death of Moore’s Law
by Michael Barger on 01-22-2016 at 12:00 pm

 For the last several years, people have predicted the end of Moore’s Law. The reasoning is that there is a limit at which one can’t shrink transistors any further. A reoccurring comment has been “You can’t divide an atom.” I had assumed that its demise would be at the hands of a new paradigm like quantum computing. Now, with Intel’s announcement that the next doubling of transistors will take 2 ½ years, it looks like it may die of old age.

I, personally, do not believe that Moore’s Law needs to die of old age. Having worked within and in support of the semiconductor industry, I believe that the scaling argument is based on a faulty assumption; that one must only use two dimensions. I also believe that the industry is finally waking up to this fact with the surge in interest in 3D integration. But it has come too late to keep the industry on the Moore’s Law curve.

I have watched as the increased cost of scaling has forced the formation of collaborative research organizations, e.g. Sematech. Chip companies have shifted market and business strategies like the fabless ecosystem. And continued M&A has resulted in massive organizations with deep pockets that make barriers to market entry by new players almost impossible. As a result, I believe that the Semiconductor industry is ripe for disruption.

When I worked at the Hughes Technology Center in the early 90’s, we were working on enabling technologies for 3D integrated circuits (3DIC). Our strategy was to freeze scaling at 0.25 micron (that’s 250 nm folks!) and build another active layer on top, doubling the circuit density. There were several technologies that we were developing to do this. For example, HRL had developed a TSV on which I was able to grow high quality silicon epitaxy. This was used to build a 3D version of a Pentium-based PC in a “cube” as demonstrator. We filed for a patent disclosure, but corporate declined to pursue.

Another development was wafer bonding and thinning. We developed a scanning plasma process that flattened the device wafer while thinning it. We had a 200mm demonstrator wafer bonded to a handle wafer that was 10nm thick with +/- 1nm variation. Obviously, 10nm is not very useful, but it meant that FDSOI was comparatively easy. Our bonding technique allowed conductors and dielectrics to be bonded, simultaneously. Our university collaborator used this process to demonstrate the fabrication of a CMOS circuit by bonding NMOS and PMOS circuits. There other technologies developed that I won’t go into for lack of reader attention. But these were only steps toward the ultimate goal, which was monolithic 3D integration.

Monolithic 3D integration was not to be the stacking of processed layers, but depositing and processing layers on a continuous process. Think in terms of transistors along with other components embedded in a matrix of dielectric with interconnects routed for optimal distances. This would require different equipment and different chemistries. One enabler we were working on was atomic layer deposition (ALD). The sub-category, atomic layer epitaxy (ALE) was the process we believed would provide the embedded transistor structures. I submitted a proposal the develop ALE silicon, which was declined just prior to GM Hughes Electronics’ demise. With Hughes’ breakup, all of these technologies have fallen into disuse. I believe that it is time to resurrect some of these concepts and develop the necessary equipment and processes to revitalize Moore’s Law.

I have an initial product concept that I would like to develop that would be an enabler to control the new processes. I am interested in finding investors who would fund the startup. If you are one or know of one, please contact me.

https://www.linkedin.com/in/mjbarger


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