SemiWiki 800x100 DAC FSWG

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                    [post_date] => 2011-11-23 05:21:00
                    [post_date_gmt] => 2011-11-23 05:21:00
                    [post_content] => Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. Sgroi et al. call "the layered-stack approach to the design of the on-chip intercore communications the Network-on-Chip (NOC) methodology." In a NoC system, modules such as processor cores, memories and specialized IP blocks exchange data using a network as a "public transportation" sub-system for the information traffic. A NoC is constructed from multiple point-to-point data links interconnected by switches (a.k.a. routers), such that messages can be relayed from any source module to any destination module over several links, by making routing decisions at the switches. A NoC is similar to a modern telecommunications network, using digital bit-packet switching over multiplexed links. Although packet-switching is sometimes claimed as necessity for a NoC, there are several NoC proposals utilizing circuit-switching techniques. This definition based on routers is usually interpreted so that a single shared bus, a single crossbar switch or a point-to-point network are not NoCs but practically all other topologies are. This is somewhat confusing since all above mentioned are networks (they enable communication between two or more devices) but they are not considered as network-on-chips. Note that some articles erroneously use NoC as a synonym for mesh topology although NoC paradigm does not dictate the topology. Likewise, the regularity of topology is sometimes considered as a requirement which is, obviously, not the case in research concentrating on "application-specific NoC topology synthesis".


An interesting white paper from Arteris: “Routing Congestion: The Growing Cost of Wires in Systems-on-Chip” demonstrates how you can drastically reduce routing congestion by using a NoC. On this picture, you can see on the left part, the routing congestion areas, highlighted through a color code (purple= very strong congestion, red=strong congestion, yellow=medium, blue=no congestion), this will sounds familiar to anybody who has already used a floor planning tool. According with Jonah Probell: “…in the process of chip design, more can be done to improve P&R wire congestion by reducing the number of wires in the IP RTL before synthesis.”




For those like me who have used floor planning tools in the mid 90’s, to help customers to release to layout the RTL version of a chip with good chance to complete the lay out phase within a decent time period (say, a couple of weeks, as these chips were designed into a supercomputer, using the largest available BiCMOS base array, running at the highest possible internal frequency, which makes sense when you design a supercomputer…), it was common to spend weeks if not MONTHS to optimize the floor plan of the IC. I realize now that having the opportunity to use a NoC at that time would certainly help us to, either reduce the design cycle (thus the Time To Market for our customer, as well as the time spent by TI FAE team), either go higher in frequency, and help our customer to launch a more powerful product. I strongly encourage anybody involved (or interested) by on the edge SoC design techniques to download this paper from Arteris here.


Eric Esteve from IPNEST




[post_title] => How to use NoC to avoid routing congestion [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => how-to-use-noc-to-avoid-routing-congestion [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:41:27 [post_modified_gmt] => 2019-06-15 02:41:27 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/how-to-use-noc-to-avoid-routing-congestion.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [1] => WP_Post Object ( [ID] => 877 [post_author] => 4057 [post_date] => 2011-11-22 19:59:00 [post_date_gmt] => 2011-11-22 19:59:00 [post_content] => Flash analog-to-digital converters (ADCs) are commonly used in high-frequency applications such as satellite communications, sampling oscilloscopes, and radar detection. Flash ADC is preferred over other ADC architectures because it is extremely fast and quite simple. However, flash ADC typically requires twice as many converters per bit for higher accuracy requirements, which increases the size of the chip (and likewise the cost).

Not surprisingly, at small process nodes, the influence of parasitic elements on these sensitive mixed-signal designs is growing, due to the increasing interactions between devices and interconnects that are in close proximity. Circuits are highly sensitive to these parasitic effects, so accurate parasitic extraction is critical for first silicon success.

Constraints used to lay out a flash ADC are also extremely important, because differential pairs must have symmetrical layouts, identical capacitors must have equal values, and resistors must be matched. For example, if one resistor must be over-etched because of process variation sensitivity, all of the resistors must be over-etched in the same way to ensure that the taps off the resistor ladder are still the correct voltage value. Several guidelines can help improve layout matching.

Designing flash ADCs requires careful tradeoffs between speed, accuracy, and power. Highly accurate parasitic extraction ensures that parasitics will not cause the ADC to behave incorrectly, and that the ADC will still meet all of the design specifications.

New 3D parasitic extraction technology applied to a flash ADC circuit design reduces the need for extra guardbanding, while ensuring the circuitry will work according to the specifications when manufactured.

You can download the complete "Reducing the Need for Guardbanding a Flash ADC Design" whitepaper HERE.

About the Author:
Karen Chow is the Technical Marketing Engineer for Calibre xRC and Calibre xACT 3D at Mentor Graphics in Wilsonville, OR. She has worked on both sides of the EDA industry, designing analog ICs and supporting EDA tool development. Karen has her BSc in electrical engineering from the University of Calgary, and her MBA from Marylhurst University. In her spare time, she enjoys playing music in bands, designing clothing and handbags, and quilting.







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 [post_title] => Reducing the Need for Guardbanding Flash ADC Designs [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => reducing-the-need-for-guardbanding-flash-adc-designs [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:54:03 [post_modified_gmt] => 2019-06-15 01:54:03 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/reducing-the-need-for-guardbanding-flash-adc-designs.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [2] => WP_Post Object ( [ID] => 876 [post_author] => 9491 [post_date] => 2011-11-22 18:16:00 [post_date_gmt] => 2011-11-22 18:16:00 [post_content] =>  David Liu receeived the Kaufman award for 2001 at the Kaufman award dinner a few weeks ago.

Or to be more formal about it:Dr. C. L. David Liu, the William Mong honorary chair professor of Computer Science and former president of the National Tsing Hua University in Hsinchu, Taiwan, will be presented with this year’s Phil Kaufman Award for Distinguished Contributions to Electronic Design Automation (EDA). Dr. C. L. David Liu, the William Mong honorary chair professor of Computer Science and former president of the National Tsing Hua University in Hsinchu, Taiwan, will be presented with this year’s Phil Kaufman Award for Distinguished Contributions to Electronic Design Automation (EDA).


Dr Liu started his career in Taiwan before coming to the US for an extended period and then returning to Taiwan where he continues to be very active in both academic circles and with his own radio program (unfortunately only in Chinese). As he says, he's a 70 year old guy living the life of two 35 year olds. Reminds me of that line when Mac is told he can't have a 42-year old scotch that night. "Give me 4 8-years olds and a 10-year old".

Jason Cong presented the award. David was Jason's PhD advisor. And not just Jason's, a long list of people who have gone on to make significant contributions to EDA. One name I recognized and hadn't known about was Anmol Mathur, who worked for me at Ambit over a decade ago and has since founded Calypto where he continues to be the CTO.

If there is one thing that characterizes David's contributions to EDA, I think it is giving heuristic algorithms rigorous foundation, or coming up with rigorous algorithms from scratch. He made major contributions in slicing floorplans, over-the-well channel routing, performance driven placement, scheduled resource sharing, optimal clock period FPGA technology mapping and rate monotonic scheduling. These are not just algorithms of historical significance, they are used inside moder EDA tools. Ajoy Bose, CEO of Atrenta, gave credit for using some of his work in SpyGlass physical. Chi-Foon Chan, COO of Synopsys gave credit for his ideas directly benefiting Astro and IC compiler. And his scheduling algorithms are used in today's cell-phones.

In 1968 David Liu wrote "Introduction to combinatorial mathematics." Remember this was before the concept of NP-completeness had been introduced, so very early in the development of combinatorial mathematics and complexity.

Perhaps most surprising of all is that since 2005, David Liu has done a weekly talk show covering all sorts of aspects of technology such as the founding of Google, Steve Jobs' now famous Stanford commencement speech.

Congratulations to David Liu.




 [post_title] => David Liu, Kauffmann Award winner [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => david-liu-kauffmann-award-winner [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:41:27 [post_modified_gmt] => 2019-06-15 02:41:27 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/david-liu-kauffmann-award-winner.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [3] => WP_Post Object ( [ID] => 875 [post_author] => 3 [post_date] => 2011-11-21 18:52:00 [post_date_gmt] => 2011-11-21 18:52:00 [post_content] => Every week I receive several webinar invitations, so the recent one from Cadence about Virtuoso Multi-Mode simulation caught my fancy because I had met with John Pierce at DAC and wanted to see what was new since then and see how they compared with Mentor and Synopsys tools.


John Pierce, Product Marketing Director

This webinar runs 41 minutes and here's what I learned:

Analog/RF Design Challenges
My favorite example is the migration to SmartPhones that now support many radios: GSM, GPRS/EDGE, UMTS/HSDBA , WLAN, GPS, Bluetooth. Last year as a late adopter I bought my first SmartPhone from Samsung, the popular Galaxy and quickly learned how limited the battery charge lasted. I'm pleased that this year I've upgraded to the Samsung inFuse and seen my batter life improve from just one day to two days between charges, even when the screen size went from 4.0" up to 4.5".


ADC Design Trends

Chip designers have tighter specs when choosing or designing analog IP, parasitics impact performance more than previous nodes, and this all leads to larger circuits that take much more simulation time for both design and verification.

MMSIM Features

  • foundry qualified/supported models for SPICE
  • cell and memory characterization (from Altos)
  • SPICE with digital, SI, PCB, RFIC and EM/IR

Spectre/Spectre RF
Make convergence and accuracy the top goals. Accept languages like: Verilog A, SpectreMDL. Support RF analysis and simulate with millions of extracted RC elements.

APS
The Accelerated Parallel Simulator can be used to reduce simulation runtimes by adding more cores in a linear fashion:

Multiple machines in a cluster are supported with: LSF, rsh, ssh, SUN GRID, Loadleveler:

Even RF simulation completes faster in APS for Shooting Newton and Envelope Analysis:


MMSIM 10.1 Release
APS got faster, RF advanced analysis added, reliability analysis added, distributed processing for faster simulation times.

UltraSim with hierarchy simulation handles an EMIR flow.

Demo by Rich Davis

Transient analysis simulation started in Analog Design Environment (ADE) using Spectre:

Same netlist was then rerun using APS on a single core, elapsed time of 6.1 seconds compared to Spectre taking 88 seconds, no loss of accuracy.


Spectre and APS waveform results compared

Use multi-threading and distributed simulation only on larger circuits.

User can trade-off between accuracy and run times, here's what happened when accuracy was loosened up the run time reduced from 6.1 to 4 seconds:


Faster but less accurate results in APS, you decide


The second APS demo circuit was bigger with 1.45 million nodes and 3+ million BSIM devices, APS, multi-threaded with 8 cores, 24K time points, ran in 4 hr​s 2 minutes 52 seconds.

The third demo circuit showed Transistor-level Envelope which simulated in 52 minutes, then Fast Envelope was simulated in under 20 seconds using pre-characterized behavioral models:



Error Vector Magnitude plotting was shown on an output node in just a few seconds:


Harmonic balance simulation results were demonstrated next on an amplifier circuit as Loadpull results where input magnitude and phase were varied across a large range in about 1 minute of time:


The final simulation showed HB noise results on a large inductor values:



Summary
It looks like Cadence has followed the parallel approach started by Magma's FineSim SPICE and FineSim Pro. Magma doesn't have their own HDL simulator, so Cadence's approach is better if you have to simulate SPICE netlists with VHDL, VHDL-AMS, Verilog-A, Verilog-AMS or Verilog.

Cadence offers UltraSim which handles hierarchy, so they're ahead of Mentor in that regard because ADiT and Eldo are flat simulators.

Synopsys has hierarchical and parallel SPICE simulation, so they go head-to-head with Cadence in this same product area.

You still have to evaluated each circuit simulation vendor on your own designs to determine if it's best for you:

  • Speed
  • Accuracy
  • Capacity
  • Integration
  • Analysis
  • Netlist compatibility
  • Learning curve
  • Price





 [post_title] => Multi-Mode Simulation - What's New at Cadence? [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => multi-mode-simulation-whats-new-at-cadence [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:39:33 [post_modified_gmt] => 2019-06-15 01:39:33 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/multi-mode-simulation-whats-new-at-cadence.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [4] => WP_Post Object ( [ID] => 872 [post_author] => 28 [post_date] => 2011-11-20 19:00:00 [post_date_gmt] => 2011-11-20 19:00:00 [post_content] => When AMD sought to shed its costly manufacturing operations, Ibrahim Ajami saw an interesting opportunity, one that promised to bring semiconductor manufacturing to Abu Dhabi. Let’s start with the January 2010 interview with Ajami, the 35 year old Chief Executive Officer of Advanced Technology Investment Company (ATIC), which is owned by the Government of the Emirate of Abu Dhabi, the controlling shareholder of GlobalFoundries (GFI).

GlobalFoundries wants 30% of the made-to-order chip market within three years. “Am I setting very aggressive targets? Yes,” Ajami said in a Jan. 28, 2010 interview in Abu Dhabi. “We need to be a $5 billion company in the next two to three years.” A 30% share would take GFI well past United Microelectronics Corp (UMC), making it the world’s second-largest contract manufacturer of chips after Taiwan Semiconductor Manufacturing Co (TSMC).

As I mentioned in TSMC versus GlobalFoundries Part I and Part II, GFI is attempting to compete head-to-head with TSMC in the first source semiconductor market, while UMC and SMIC are content to be second and third source semiconductor manufacturers. GFI has not been shy about their challenge to TSMC’s wafer supremacy and TSMC has responded in kind by increasing capital expenditures, increasing R&D expenses, and hiring thousands of engineers.

Unfortunately it has not quite worked out as planned. As reported by the Albany NY Times Union: GlobalFoundries delays fab plans, construction of facility in Abu Dhabi put on hold; Malta expansion in doubt” due to the "uncertain global economic outlook"? As reported on SemiWiki last week by Bill Jewell of Semiconductor Intelligence: Semiconductor market to grow 3% in 2011, 9% in 2012. I agree with Bill, 2012 will be a significant semiconductor growth year, so I’m not buying the uncertain global semiconductor economic outlook excuse. To me, this is a case of poorly set expectations and as a result, a failure to implement.

GlobalFoundries partner and number one customer AMD recently blamed a revenue shortfall on “continued 32nm manufacturing issues” which resulted in shortages of the Llano APU. AMD Q3 revenue growth was closer to 5% versus the forecasted 10% with lower margins than expected. Other AMD products have been delayed, some products have been moved to TSMC. The blame again falls on GFI's inability to deliver.

This is an interesting dynamic since AMD and GlobalFoundries share board members and equity. The 32nm manufacturing facilities in question belonged to AMD (Dresden) as do the employees that run them, so they are in effect pointing the blame finger at themselves. But since AMD is a publicly traded company and GlobalFoundries is private, rhetoric to boost AMD stock value is a net gain.

Meanwhile GlobalFoundries and AMD are both doing the executive shuffle with new CEOs and other key infrastructure members. Several of the GlobalFoundries guys now work for the foundry group at Intel, which is interesting. Comments on LikedIn thus far are running negative:

"Has the "Energy" money tap been turned off for the Semiconductor industry? GloFo is asking for more money? "A proposed second fab in Malta is also off the table, the company says, unless New York State officials approve even more financial assistance." Maybe it’s just politics, either way, interesting development (or lack thereof)."David Bethke

"This is too bad but not completely unexpected. Considering the current world market it is a huge task to try to open several phases of the NY fab and a completely new one in an area of the world where there is little semiconductor manufacturing experience."Stephen Griffing

You forgot to add: "due to flooding in Thailand", "due to inept executive management", and "due to unreasonable shareholder expectations, reducing corporate reinvestment and key employee acquisition and retention."Andy Turudic

I will dig deeper in the coming weeks. Let me know what you think of GFI's prospects moving forward and I will keep you posted on what I find out.

Note: You must be logged in to read/write comments.




 [post_title] => GlobalFoundries' Expansion on Hold! Trouble in Abu Dhabi? [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => globalfoundries-expansion-on-hold-trouble-in-abu-dhabi [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:41:25 [post_modified_gmt] => 2019-06-15 02:41:25 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/globalfoundries-expansion-on-hold-trouble-in-abu-dhabi.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [5] => WP_Post Object ( [ID] => 874 [post_author] => 3 [post_date] => 2011-11-19 16:42:00 [post_date_gmt] => 2011-11-19 16:42:00 [post_content] => The IEEE has an Orange Country Chapter of the Components, Packaging and Manufacturing Technology Society who are organizing an all-day workshop, 3D Integrated Circuits: Technologies Enabling the Revolution. This looks to be an informative day with real-world examples in both design and test being presented by over a dozen experts. Registration details are here.

Our semiconductor industry is challenged to continually reduce product costs while simultaneously increase user features and lengthen battery life, all at a profit. 3D IC design and test is one method to satisfy these challenges.

Agenda




Welcome & Introduction
09:00 –09:05am
Session –1: Market, Architecture & Design




Opportunities and Challenges for 3D Integrated Heterogeneous Electronic Systems
09:05 –09:35am
Prof. Muhannad Bakir, Integrated 3D Systems Group, Georgia Tech, Atlanta, GA

Economics to Drive 3D Stacking
09:35 –10:05am
Dr. Phil Garrou, Microelectronic Consultants of North Carolina, Research Triangle Park, NC

Stack Silicon Interconnect Development and Key Role of Supply Chain Collaboration
10:05 –10:35am
Dr. Suresh Ramalingam, Sr. Director, Xilinx, San Jose, CA

Break
10:35 –10:45am

Emerging Challenges for Power, Signal, and Reliability Verification on 3D-IC/Silicon Interposer Designs
10:45 –11:15am
Dr. Norman Chang, Co-Founder, Apache Design Systems, Ansys, San Jose, CA

3D IC Test Challenges and Solutions
11:15AM to 11:45AM
Dr. Stephen Pateras
Product Marketing Director, Silicon to Test, Mentor Graphics

3D IC offers a compelling alternative to traditional scaling for achieving advances in performance, reduced power consumption, cost reduction, and increased functionality in a small package. Unfortunately 3D IC packaging also creates some new challenges for manufacturing test. Wafer sort will need to deliver higher test quality to ensure acceptable final package yields and thus limit the cost impact of stacking bad die in a 3D package. Stacked die also create significant test access problems since the die-level I/O may not be accessible from within the package. Ensuring that all inter-die TSV connections are adequately tested further complicates the overall test problem. This presentation will review test solutions available to cost-effectively test 3D ICs from wafer sort to packaged assembly.

Testing Challenges: higher Known Good Die (KGD), memory-on-logic configurations, logic-on-logic testing


Typical SOC with an approach to testing each block


Testing a Memory die stacked on logic

White Paper on 3D-IC testing.


Presentation Title to be announced
11:45 –12:15pm
A. La Manna, K. Rebibis, Dr. Eric Beyne, Dr. B. Swinnen, IMEC, Leuven, Belgium

Lunch
12:15 –01:15pm


Session –2: Manufacturing Technologies & Materials




Cost-Effective 3D Semiconductor Packaging Solutions Based on Embedded Die in Laminate Technology
01:15 –01:45pm
Ted Tessier, Senthil Sivaswamy, Flip Chip International LLC, Phoenix, AZ, Dr. Kazuhisa Itoi, Fujikura Ltd, Tokyo, Japan

Challenges and Solutions in Mid-end and Back-end Processes for 2.5D and 3D TSV – an OSAT Perspective
01:45 –02:15pm
Dr. YeongLee, Product and Tech. Marketing Director, STATS ChipPAC, Fremont, CA

Advanced Underfillsfor 2.5D and 3D Applications
02:15 –02:45pm
Dr. Rose Guino, Dr. Betty Huang, Dr. Kevin Becker, Dr. T. Takano, Henkel Electronic Materials, LLC, Irvine, CA

Break
02:45 –03:00pm
3D TSV Interposer and its Applications
03:00 –03:30pm
Dr. GS Kim, Founder & CEO, EPWorks, Ltd. Seoul, Korea
Via Reveal –High rate Si Thinning and Low Temperature Dielectrics for Post-TSV Processing03:30 –04:00pm
David Butler, Vice President –Marketing, SPTS Technologies, Newport, UK

Vote of Thanks
04:00 –04:05pm




 [post_title] => Learning about 3D IC Design and Test, IEEE Workshop on Friday, December 9th in Newport Beach, CA [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => learning-about-3d-ic-design-and-test-ieee-workshop-on-friday-december-9th-in-newport-beach-ca [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:41:22 [post_modified_gmt] => 2019-06-15 02:41:22 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/learning-about-3d-ic-design-and-test-ieee-workshop-on-friday-december-9th-in-newport-beach-ca.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [6] => WP_Post Object ( [ID] => 871 [post_author] => 4 [post_date] => 2011-11-17 10:03:00 [post_date_gmt] => 2011-11-17 10:03:00 [post_content] => Denali acquisition by Cadence in May 2010, ChipIdea, Virage Logic, and nSys acquisitions by Synopsys in 2009, 2010 and 2011 (resp.) shows that IP market is consolidating... but new IP vendors are still emerging! So we need to know on which product the Interface IP market leader will tend to a dominant position, which new products will be added to their port-folio, what could be the new strategy from the well known EDA challenger in Interface IP and Verification IP, and get information about the new comers, or IP vendors start supporting emerging protocols…

The use of High Speed Serial Interconnect instead of parallel interface is becoming the preferred solution for new products developed across various segments. In this survey, we study the Interface IP market, looking at all the existing protocols: PCIe, USB (HS & SuperSpeed), Serial RapidIO, Infiniband, Hyper Transport, SATA, Fibre Channel, HDMI, Ethernet, XAUI, Display Port, MIPI and DDRn, and extracting the most promising in term of long term growth. To understand the market, we first analyze for every selected IP segment, the market share, growth rate and positioning of the different vendors, for 2005-2010. Then, we propose a market forecast on the period 2011-2015.




We can see on the above picture the negative impact of the Q4 2008-Q1/Q2/Q3 2009 recession on the growth rate for every segment – except DDRn Memory Controller. Even if in 2010, the market has recovered, we should come back to 20-30% like growth rate only in 2011. In the survey, we have made an analysis, by protocol standard (USB, USB 3.0, PCIe, SATA, DDRn, HDMI) of the market evolution from 2005 to 2010, detailing the revenue by vendors, like we can see on this example for PCIe IP:






What will happen in the future depends, as always, of the health of the global economy. Assuming no catastrophic event, 2010/2011 growth should continue in 2012, and the interface IP market should reach a $350M level, or be 58% larger than in 2009 (a 17% CAGR during these 3 years). The reasons for growth are well known (at least for those who read Semiwiki frequently!): the massive move from parallel I/Os to high speed serial, the ever increasing need for more bandwidth, not only in Networking, but also in PC, PC peripheral, Wireless and Consumer Electronic segments – just because we (the end user) exchange more data through Emails, Social Media, watch movies or listen music on various, and new, electronic systems. Also because these protocols standards are not falling in commoditization (which badly impact the price you sell Interface IP), as the various organizations (SATA, USB, PCIe, DDRn to name the most important) are releasing new protocol version (PCIe gen-3, USB 3.0, SATA 6G, DDR4) which help to keep high selling price for the IP. For the mature protocols, the chip makers expects the IP vendors to port the PHY (physical part, technology dependant) on the latest technology node (40 or 28 nm), which again help to keep price in the high range (half million dollar or so). Thus the market growth will continue, at least for the next three to four years.





On the long term, the Interface IP revenue is expected to double on 2015/2009 periods, going from $220M in 2009 up to $450M in 2015, growing at a 12.4% CAGR. In the same period, the Semiconductor market, like any mature market, will tend to rationalize his sourcing strategy. Instead of having to select a different IP vendor for every different interface standard, or even for the PHY and the Controller for a given standard, an IDM or Fabless will prefer the one stop shop concept, at least for a family of IP like the wired Interface IP. This one stop shop concept will be extended to Verification IP, to be offered by traditional IP vendors.

As of today, there is one market leader: Synopsys. Instead of inventing a standard, or to invest upfront, the company has grown through successive acquisition of small, focused and successful IP vendors. This is true with USB, PCIe, DDR and HDMI! And they are now number one and ultra dominant in USB, dominant in PCIe, number one in SATA, number one in DDRn, and starting in HDMI and MIPI. Their key strength is their worldwide direct sales network, able to reach every design team in the world (thanks to their logic synthesis tool), and their ability to provide each of the Top 5 standard based IP. Initially, the one stop shop concept was developed by "generic IP" vendors, like CAST, to sell commodity functions. Since 2009, we can see Synopsys as the one stop shop company selling highly specific, complexes Interface IP like USB 3.0, PCIe Gen-3, SATA II and III, HDMI and DDR3. Thus we expect Synopsys to lead this market in 2015, like they did it in 2009, where they enjoyed $83M or 38% market share on Interface IP or 2010 with $100+ million and more than 40% market share.

Is there is room for another IP vendor competing with Synopsys?We think there is still room for another IP vendor to compete on the Interface IP segment (the market does not like to have such a reduce choice). In the past, Mentor Graphics has tried to build an IP port-folio, to finally exit the market. Nevertheless, two EDA vendors (Cadence and Mentor Graphics) have a key strength that you absolutely need to be successful on the IP market: a worldwide sales force able to have access to almost every design team in the world. They also get enough cash to grow by acquisition (like did Synopsys, in fact)! Such a new comer should remember that he will have to provide an integrated solution. This means he will have to manage both the Digital (Controller) part of the IP and the Analog (PHY) and probably also the software drivers. Talking about Cadence, if they want to be present on this IP market which represent already several $100M and will grow at a 12% CAGR from 2010 to 2015; we would expect a next step after Denali acquisition! It would be to acquire one (or several) IP vendor strong in Interface IP in general (Denali is strong in DDRn but very weak everywhere else) and be able to propose a wide PHY IP port-folio. They could develop a PHY product line from scratch, but this is far to be the easiest way.


Finally, what could be the challenges for the wired interface IP market itself?We have seen that the decline in ASSP/ASIC design starts, which is real, is more than compensated by two distinct effects. The SoC proportion of ASIC/ASSP is enough growing and generating new needs for Memory Interface and High Speed Serial Interconnect to compensate this decline. The second effect is the high demand for Data bandwidth in the PC and Consumer Electronics markets, which can only be satisfied by moving from the old, parallel based, interconnect link to the High Speed Serial Interconnect. The availability of serial protocols, like USB, PCIe, HDMI, MIPI and SATA, allows the pervasion into multiple applications, in various market segments, so the number of design starts including these IP is growing. Finally, the emergence of ThunderBolt, promoted by Intel, could perturb the market, probably not now but in the mean term. If this standard is really used, what will happen to the PHY IP vendors for protocols like USB 3.0, HDMI or eSATA? As a matter of fact, the decision from Intel to delay up to Q2 2012 the integration of USB 3.0 into the PC chip set was not good news for the USB 3.0 IP vendors.


Another challenge could be the relationship between the IP vendors and the Silicon foundries. In fact, the interface IP, and more specifically the PHY IP, has become a function present in almost every design, which can be seen by the foundries as a hook to keep a customer locked with their technology. The FPGA vendors were the first to understand it, and they license IP not to generate IP sales, but to lock their customer to their technology. It will be interesting to monitor what will be the strategy of the Silicon foundries in respect with the (PHY) interface IP vendors in the future.


Eric Esteve from IPNEST – Table of Content for “Interface IP Survey 2005-2010 - Forecast 2011-2015” available here [post_title] => A tribute to Research on Interface IP Market [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => a-tribute-to-research-on-interface-ip-market [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:41:20 [post_modified_gmt] => 2019-06-15 02:41:20 [post_content_filtered] => [post_parent] => 0 [guid] => https://35.226.139.164/uncategorized/871-a-tribute-to-research-on-interface-ip-market/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [7] => WP_Post Object ( [ID] => 870 [post_author] => 9491 [post_date] => 2011-11-16 22:22:00 [post_date_gmt] => 2011-11-16 22:22:00 [post_content] =>  Intel has been making a little bit of a PR fuss about the 40th anniversary of the microprocessor. And they are entitled to. The Intel 4004 was the first customer-programmable chip. Of course if you look at it's capabilities today they are laughably minimal, and even looking at the chip, a 16-pin DIP (dual-in-line-package for anyone under about 40, pins down both sides of a plastic or ceramic package). Here's a picture of what it looked like . Microprocessor? Not on a thousand pin BGA?

 Federico Fagini and Ted Hoff designed it and there are some great quotes from them as the first silicon fails but the second turn works. Most people in tech know the story that a company in Japan, Busicom, contracted Intel to build a calculator chip but they worked out that the best way to do that was to design a programmable device and then program it to be a calculator. But like so many design projects it was late. Fagini got drafted into the project his first day at Intel when an engineer from Busicom showed up to check how the project was going:

Masatoshi Shima: You bad! You bad!
Faggin: I just arrived here! I just was hired yesterday!
Masatoshi Shima: You late!


This was ages before personal computers. As Ted Hoff said:

At that time, it didn't really make sense to talk about personal computers.

Three years and four chip generations later we arrived at the 8088 which was the heart of the original PC. One or two floppy disks, back when they really were floppy. Or even none, you could use cassettte tape if you couldn't afford those expensive disks.

But even Gordon Moore was somewhat unconvinced:

I was Chief Executive at Intel I remember one of our young engineers coming in and describing how you could build a little computer for the home. I said gee that‘s fine. What would you use it for?‘ And the only application he could think of was housewives putting their recipes on it. I didn‘t think that was going to be a very powerful application.


And over at Digital, then chairman Ken Olsen made his famous remark in 1977:

I see no reason for any individual to have a computer in his home.

That has to be up there with Watson's quote at IBM that he only saw a market for 5 computers. ARM ships billions every year. A million PCs, roughly, ship every day.

But, as I've said repeatedly, power is the big problem. Here's Justin Ratner, Intel's CTO:

Today, a petaFLOPS computer is burning somewhere between five and seven megawatts. So if we just scaled it up by 1000x it would be in the gigawatt range and I‘d have to buy everyone a nuclear reactor to run that machine; maybe a couple of nuclear reactors.

But he's optimistic:

The sheer number of advances in the next 40 years will equal or surpass all of the innovative activity that has taken place over the last 10,000 years of human history.

At this point, it‘s fair to ask, what lies ahead? What lies beyond multi-core and many- core computing? And the answer... is called extreme-scale computing. This is multi- core and many-core computing at the extremes. Our 10 year goal here is to achieve nothing modest: a 300x improvement in energy efficiency for computing at the extremes.

As Dan Hutcheson of VLSI Research said:

The roots of all things smart, personal and mobile is the Intel 4004.

And I think he's right.




 [post_title] => Happy 40th birthday microprocessor [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => happy-40th-birthday-microprocessor [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:41:20 [post_modified_gmt] => 2019-06-15 02:41:20 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/happy-40th-birthday-microprocessor.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [8] => WP_Post Object ( [ID] => 869 [post_author] => 12 [post_date] => 2011-11-16 21:00:00 [post_date_gmt] => 2011-11-16 21:00:00 [post_content] => The outlook for the global semiconductor market in 2011 has deteriorated from earlier in the year due to multiple factors including slower than expected economic growth in the U.S., debt crises in Europe and the Japan earthquake and tsunami. Recent forecasts have narrowed down to a range of -1.4% to 3.5%. In the first half of 2011, forecasts ranged from 5% to 10%. 2012 growth is expected to improve over 2011, with a range of 3.4% to 10.4%.



WSTS has released data on the semiconductor market through 3Q 2011. Thus year 2011 growth will be determined by growth in 4Q 2011. The mid-points of key company guidance for 4Q 2011 revenue growth vary widely. Microprocessor companies Intel and AMD expect growth of about 3%. Qualcomm’s mid point is 10%. Texas Instruments and STMicroelectronics, which are largely analog, expect declines of 2% and 9%, respectively. The major Japanese semiconductor companies are continuing to bounce back from the March earthquake and tsunami. 3Q11 revenue growth over 2Q11 (in yen) was 21% for Toshiba’s semiconductor business and 17% for Renesas Electronics. Based on revenue forecasts for the fiscal year ending March 2012 and assuming the same growth rates for 4Q11 and 1Q12, Toshiba’s 4Q11 semiconductor revenue growth is estimated at 24% and Renesas is estimated at 4%.

We at Semiconductor Intelligence have developed three scenarios for 4Q11 and year 2011 semiconductor revenue growth which we believe encompass the likely alternatives. As shown in the table below, the lowest case is no growth in 4Q11, leading to 2.3% annual growth. The middle case results in 3% growth in 2011 and the high case results in 3.5% growth. Our official forecast is 3% growth in 2011 and 9% in 2012, one percentage point lower in each year from our August forecast.


Why are our forecasts for 2011 and 2012 semiconductor market growth at the high end compared to other forecasters? The answer is demand for electronics remains healthy despite global economic problems. The chart below shows worldwide unit shipment change versus a year ago based on data from IDCand Strategy Analytics. Mobile phone growth has moderated to 11% to 12% growth in 2Q11 and 3Q11 after a strong recovery from the recession. PC growth has slowed significantly, with a decline in 1Q11 and growth in the 3% to 4% range for the last two quarters. Some of the slowdown in PC growth can be attributed to the rapid rise of media tablets, such as the Apple iPad. For many users, a media tablet is a replacement for a PC. Adding media tablet units and PC units results in higher growth for the combination, in the 14% to 17% range for the last two quarters. Thus growth in mobile phones and in PCs + media tablets has been double digit in 2Q11 and 3Q11, similar to growth rates in the first halfof 2008 prior to the global financial crisis.



Semiconductor Intelligence, LLC can perform a variety of services to provide you and your company with the intelligence needed to compete in the highly volatile environments of the semiconductor and electronics markets.




 [post_title] => Semiconductor market to grow 3% in 2011, 9% in 2012 [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => semiconductor-market-to-grow-3-in-2011-9-in-2012 [to_ping] => [pinged] => [post_modified] => 2019-06-14 21:41:18 [post_modified_gmt] => 2019-06-15 02:41:18 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/semiconductor-market-to-grow-3-in-2011-9-in-2012.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [9] => WP_Post Object ( [ID] => 865 [post_author] => 28 [post_date] => 2011-11-16 10:06:00 [post_date_gmt] => 2011-11-16 10:06:00 [post_content] => The Nintendo Wii is one of the most successful gaming platforms with the most diverse set of games -- from fun games that can be enjoyed by the whole family to fitness programs that can be used by adults. They beat the dominant Sony Playstation and the Microsoft Xbox by thinking outside the box and creating a platform that was really easy to use and powerful enough to create the wide range of ‘games’.

When playing a game on the Wii with my son, I had the thought that probably the first really successful gaming platform was a deck of playing cards. (In retrospect, I should probably not have verbalized my thought because it brought teenage laughter and derision, unwarranted in my opinion). Unlike other board games, the playing card is a true platform that has spawned thousands of games played by young and old in every corner of the world. While games like Trivial Pursuit or Sudoku may enjoy intense popularity for a period of time, the interest will eventually fade. However, playing cards will continue to be forever because new games and variations can be invented by anyone.

The power of platforms has most recently been demonstrated by Apple and Google. Nokia and Blackberry created devices that did a few things very well and were wildly successful for a period of time. Apple and Google trumped them by creating powerful platforms in the iOS and Android, thus unleashing the creativity of millions of developers to create hundreds of thousands of applications that no single company could even imagine, much less develop.

Extensible platforms not only allow third parties to expand and enhance your product offering, they also provide customers the power to customize and control their own user experiences. This is particularly true in technical and complex areas, such as EDA, where each design team has unique requirements and a cookie cutter application would not be feasible. An extensible platform adds new functionality from third parties to your product, making it more appealing to new customers. It also makes your product much more ‘sticky’ because once customers customize and integrate it into their flow, it is that much less likely that it would replace your product with another competing product without a REALLY good reason.

EDA vendors have long realized the power of the platform and the need for extensibility. One very successful platform that I am quite familiar with is Cadence Virtuoso. With the powerful Skill extension language Cadence has created a strong ecosystem of third party products that integrate and enrich the Virtuoso flow beyond anything that Cadence could invent or implement on its own. The millions of lines of Skill code written by customers and partners virtually ensures the dominance of Virtuoso for years to come despite strong new competition from several major EDA vendors.

This brings me to DAC 2011. Some of our competitors were talking about a new application -- IP management. It seems that someone was using long-legged, provocatively clad women to try to build a buzz about IP management. We know that several of our customers are managing and sharing IP blocks and PDKs across multiple projects using ClioSoft SOS Enterprise Edition hardware configuration management (HCM) platform. Did we miss the marketing boat?

What do you really need to manage your IP? Broadly speaking, you need to be able to manage and version control your IP, allow users across the enterprise to browse and search for IP based on functionality and attributes such as technology or foundry (preferably with a web browser), view datasheets or compare IP to help select the right one, re-use and track usage of the IP, get notifications about new revisions, easily upgrade if necessary, and track and report issues – all while making sure that access is controlled.

ClioSoft's SOS platform already has all the underlying functionality and it has been in use for years:


  • Reference, reuse, track, and update IP
  • Customize and manage any attributes
  • Web interface to browse and search for IP based on attributes
  • Integration with issue tracking systems
  • Comprehensive access controls
  • Patented Universal DM Adaptor to manage composite objects

One customer who dropped by our booth at DAC told us that he is already managing IP on the SOS platform and did not understand what all the hype was about. He came by to request a few changes to SOS to make it even better. Since ClioSoft owns the SOS HCM platform and does not rely on third party software configuration management systems to do the heavy lifting, we were able to add the suggested enhancements quickly.

We realized that what we were missing was an ‘app’ to better demonstrate how to use the SOS platform to manage IP. By defining the right set of attributes and adding some custom GUI elements, in just a few days, we were able to build our own ‘app’ to demonstrate how the production-proven SOS platform can be used to manage and reuse IP across the enterprise. Since every design team has a different interpretation of what IP is and how it should be managed, an open application built on the SOS platform allows customers to easily customize the interface, attributes, and flow to mange and reuse IP. Customers are not forced to adopt a methodology built into an IP management application. Instead the SOS platform is easily adapted to meet customers’ needs.

The power of the platform – a robust and custom IP management solution in just days. Request an SOS platform demonstration HERE.

by Srinath Anantharaman, founder and CEO of ClioSoft




 [post_title] => The Power of the Platform! [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => closed [post_password] => [post_name] => the-power-of-the-platform [to_ping] => [pinged] => [post_modified] => 2019-06-14 20:54:02 [post_modified_gmt] => 2019-06-15 01:54:02 [post_content_filtered] => [post_parent] => 0 [guid] => https://www.semiwiki.com/word5/uncategorized/the-power-of-the-platform.html/ [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) ) [post_count] => 10 [current_post] => -1 [in_the_loop] => [post] => WP_Post Object ( [ID] => 878 [post_author] => 4 [post_date] => 2011-11-23 05:21:00 [post_date_gmt] => 2011-11-23 05:21:00 [post_content] => Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. Sgroi et al. call "the layered-stack approach to the design of the on-chip intercore communications the Network-on-Chip (NOC) methodology." In a NoC system, modules such as processor cores, memories and specialized IP blocks exchange data using a network as a "public transportation" sub-system for the information traffic. A NoC is constructed from multiple point-to-point data links interconnected by switches (a.k.a. routers), such that messages can be relayed from any source module to any destination module over several links, by making routing decisions at the switches. A NoC is similar to a modern telecommunications network, using digital bit-packet switching over multiplexed links. Although packet-switching is sometimes claimed as necessity for a NoC, there are several NoC proposals utilizing circuit-switching techniques. This definition based on routers is usually interpreted so that a single shared bus, a single crossbar switch or a point-to-point network are not NoCs but practically all other topologies are. This is somewhat confusing since all above mentioned are networks (they enable communication between two or more devices) but they are not considered as network-on-chips. Note that some articles erroneously use NoC as a synonym for mesh topology although NoC paradigm does not dictate the topology. Likewise, the regularity of topology is sometimes considered as a requirement which is, obviously, not the case in research concentrating on "application-specific NoC topology synthesis".


An interesting white paper from Arteris: “Routing Congestion: The Growing Cost of Wires in Systems-on-Chip” demonstrates how you can drastically reduce routing congestion by using a NoC. On this picture, you can see on the left part, the routing congestion areas, highlighted through a color code (purple= very strong congestion, red=strong congestion, yellow=medium, blue=no congestion), this will sounds familiar to anybody who has already used a floor planning tool. According with Jonah Probell: “…in the process of chip design, more can be done to improve P&R wire congestion by reducing the number of wires in the IP RTL before synthesis.”




For those like me who have used floor planning tools in the mid 90’s, to help customers to release to layout the RTL version of a chip with good chance to complete the lay out phase within a decent time period (say, a couple of weeks, as these chips were designed into a supercomputer, using the largest available BiCMOS base array, running at the highest possible internal frequency, which makes sense when you design a supercomputer…), it was common to spend weeks if not MONTHS to optimize the floor plan of the IC. I realize now that having the opportunity to use a NoC at that time would certainly help us to, either reduce the design cycle (thus the Time To Market for our customer, as well as the time spent by TI FAE team), either go higher in frequency, and help our customer to launch a more powerful product. I strongly encourage anybody involved (or interested) by on the edge SoC design techniques to download this paper from Arteris here.


Eric Esteve from IPNEST




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How to use NoC to avoid routing congestion

How to use NoC to avoid routing congestion
by Eric Esteve on 11-23-2011 at 5:21 am

Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. Sgroi et al. call “the layered-stack approach to the design of the on-chip intercore communications the Network-on-Chip (NOC) methodology.” In a NoC system, modules such as processorRead More


Reducing the Need for Guardbanding Flash ADC Designs

Reducing the Need for Guardbanding Flash ADC Designs
by SStalnaker on 11-22-2011 at 7:59 pm

Flash analog-to-digital converters (ADCs) are commonly used in high-frequency applications such as satellite communications, sampling oscilloscopes, and radar detection. Flash ADC is preferred over other ADC architectures because it is extremely fast and quite simple. However, flash ADC typically requires twice as many… Read More


David Liu, Kauffmann Award winner

David Liu, Kauffmann Award winner
by Paul McLellan on 11-22-2011 at 6:16 pm

David Liu receeived the Kaufman award for 2001 at the Kaufman award dinner a few weeks ago.

Or to be more formal about it:Dr. C. L. David Liu, the William Mong honorary chair professor of Computer Science and former president of the National Tsing Hua University in Hsinchu, Taiwan, will be presented with this year’s Phil Kaufman Award… Read More


Multi-Mode Simulation – What’s New at Cadence?

Multi-Mode Simulation – What’s New at Cadence?
by Daniel Payne on 11-21-2011 at 6:52 pm

Every week I receive several webinar invitations, so the recent one from Cadence about Virtuoso Multi-Mode simulation caught my fancy because I had met with John Pierce at DAC and wanted to see what was new since then and see how they compared with Mentor and Synopsys tools.


John Pierce, Product Marketing Director

This webinar runs… Read More


GlobalFoundries’ Expansion on Hold! Trouble in Abu Dhabi?

GlobalFoundries’ Expansion on Hold! Trouble in Abu Dhabi?
by Daniel Nenni on 11-20-2011 at 7:00 pm

When AMD sought to shed its costly manufacturing operations, Ibrahim Ajami saw an interesting opportunity, one that promised to bring semiconductor manufacturing to Abu Dhabi. Let’s start with the January 2010 interview with Ajami, the 35 year old Chief Executive Officer of Advanced Technology Investment Company (ATIC), … Read More


Learning about 3D IC Design and Test, IEEE Workshop on Friday, December 9th in Newport Beach, CA

Learning about 3D IC Design and Test, IEEE Workshop on Friday, December 9th in Newport Beach, CA
by Daniel Payne on 11-19-2011 at 4:42 pm

The IEEE has an Orange Country Chapter of the Components, Packaging and Manufacturing Technology Society who are organizing an all-day workshop, 3D Integrated Circuits: Technologies Enabling the Revolution. This looks to be an informative day with real-world examples in both design and test being presented by over a dozen … Read More


A tribute to Research on Interface IP Market

A tribute to Research on Interface IP Market
by Eric Esteve on 11-17-2011 at 10:03 am

Denali acquisition by Cadence in May 2010, ChipIdea, Virage Logic, and nSys acquisitions by Synopsys in 2009, 2010 and 2011 (resp.) shows that IP market is consolidating… but new IP vendors are still emerging! So we need to know on which product the Interface IP market leader will tend to a dominant position, which new products… Read More


Happy 40th birthday microprocessor

Happy 40th birthday microprocessor
by Paul McLellan on 11-16-2011 at 10:22 pm

Intel has been making a little bit of a PR fuss about the 40th anniversary of the microprocessor. And they are entitled to. The Intel 4004 was the first customer-programmable chip. Of course if you look at it’s capabilities today they are laughably minimal, and even looking at the chip, a 16-pin DIP (dual-in-line-package … Read More


Semiconductor market to grow 3% in 2011, 9% in 2012

Semiconductor market to grow 3% in 2011, 9% in 2012
by Bill Jewell on 11-16-2011 at 9:00 pm

The outlook for the global semiconductor market in 2011 has deteriorated from earlier in the year due to multiple factors including slower than expected economic growth in the U.S., debt crises in Europe and the Japan earthquake and tsunami. Recent forecasts have narrowed down to a range of -1.4% to 3.5%. In the first half of 2011,Read More


The Power of the Platform!

The Power of the Platform!
by Daniel Nenni on 11-16-2011 at 10:06 am

The Nintendo Wii is one of the most successful gaming platforms with the most diverse set of games — from fun games that can be enjoyed by the whole family to fitness programs that can be used by adults. They beat the dominant Sony Playstation and the Microsoft Xbox by thinking outside the box and creating a platform that was really… Read More