SEMI’s Strategic Materials Conference is coming up fast, on September 30th and October 1st next week at the Biltmore in Santa Clara. This year’s theme, Materials Matter—Enabling the Future of IC Fabrication and Packaging, will take a broad look at what is driving the demand for new materials, and how material suppliers … Read More
Siemens EDA Makes 3D IC Design More Accessible with Early Package Assembly Verification2.5D and 3D ICs present special challenges since…Read More
Webinar: Fine-grained Memory Protection to Prevent RISC-V Cyber AttacksMost organizations are aware of cybercrime attempts such…Read More
Webinar: Samtec and Achronix Expand AI in the Data CenterThe performance demands of data centers continue to…Read More
Don't Settle for Less Than Optimal - Get the Perfect Inductor Every TimeThe meaning of the word “Veloce” is “blazing…Read More
Synopsys is Paving the Way for Success with 112G SerDes and BeyondData communication speeds continue to grow. New encoding…Read More
The Must Read FPGA Book – Secrets Inside
Crockett, Elliot, Enderwitz & Stewart is not a law firm, thank goodness… what you’ll find is that these folks are the authors of the world famous book entitled, now hold on here for a title, this is a creative one “The Zynq Book”, It is free, get your download here. Every designer should have this book no matter what FPGA parts they… Read More
Explaining HAPS-DX in an elevator
Every development team has been through this challenge: finding a tool that looks fantastic, then heading off to the manager one or two levels up who has enough signature authority for the purchase order. Signatures for amounts reading more than a couple of trailing zeros on POs are rarely free, or painless. … Read More
AMD Design IP Deal with Virage Logic… Oops… Synopsys
Whoever has said that history never repeats itself should read this recent PR from AMD! The news can be summarized in three points:
- Multi-year agreement gives AMD access to a range of Synopsys design IP including interface, memory compiler, logic library and analog IP for advanced FinFET process nodes
- Synopsys acquires rights
The TSMC iPhone 6!
Fortunately Paul McLellan and I missed IDF. Paul was atop Mt. Kilimanjaro and I was in Taiwan signing books. After reviewing the materials and watching the videos we really didn’t miss much in regards to mobile so no regrets. The Apple event would have been fun even though I won’t be buying an iPhone6 or an iWatch and I will tell you why.… Read More
Really Apple? Tanazania Leads US in Mobile Payments
I was in Tanzania a few weeks ago. One of the conceits that we have in the US is that we lead the world in technology. That is true in many areas but in mobile the US is a laggard. Just look at the fuss made about NFC payments in the new iPhone given that Japan had mobile payments over a decade ago.
Another area where the US is a laggard, or maybe… Read More
Samsung 14nm FinFET Design with Cadence Tools
The first consumer products with 20nm processing are arriving in 2014 like the 2 billion transistor A8 chip in the iPhone 6, however at the 14nm node there are new designs underway to continue the trend of Moore’s Law. To get a better feel for the challenges of designing with 14nm FinFET technology I watched a 23 minute video … Read More
Expansion at Calypto through Real Value Addition in SoC Design
When we get the notion of expansion of a company, it always provides a positive picture about something good happening to boost that expansion. There can be several reasons for expansion such as merger & acquisition, formation of joint venture or partnership, large customer orders and so on. However, organic expansion which… Read More
Is Number of Signoff Corners an Issue?
Semiconductor companies continue to use the traditional corner-based signoff approach that has been developed more than 40+ years ago and has since remained mainly unchanged as an industry paradigm. Initially it had 2 corners, namely Worst Case (WC) and Best Case (BC) with the maximum and minimum cell delay respectively. Note… Read More
Xilinx UltraScale leads the way on connectivity
Even though Xilinx FPGAs seem to keep growing in densities and gobbling up boards into a single part, there is still the need for chip to chip connectivity and of course backplane connectivity. Xilinx 20nm UltraScale, TODAY, can really move 28 gb/s over the back plane. This is something that you cannot do with Altera 20nm, they are… Read More
Application-Specific Lithography: Sense Amplifier and Sub-Wordline Driver Metal Patterning in DRAM