As the semiconductor consolidation continues and thousands of semiconductor professionals update their LinkedIn profiles, the march to create new silicon opportunities is increasing at a rapid pace. It is 1980s deja vu all over again when the fabless business model reenergized the semiconductor industry and brought affordable… Read More
Revolutionizing Simulation Turnaround: How Siemens’ SmartCompile Transforms SoC VerificationIn the race to deliver ever-larger SoCs under…Read More
Arteris Simplifies Design Reuse with Magillem PackagingMany know Arteris as the “network-on-chip”, or NoC,…Read More
Tensilica 4th generation DSP IP is a VPU
You may not know Tensilica DSP IP core, but you probably use Tensilica DSP powered systems in your day to day life. Every year, over 2 billion DSP cores equip IC in thousands of designs supporting IoT, Mobile Phones, Storage/SSD, Networking, Video, Security, Cameras… and more. Why DSP processing, the foundation of all Tensilica… Read More
Meeting DFM Challenges with Hierarchical Fill Data Insertion
To describe the latest methodology for the addition of Design for Manufacturability fill shapes to design layout data, it’s appropriate to borrow a song title from Bob Dylan – The Times They Are A Changin’. The new technical requirements are best summarized as: “The goal is now to add as much fill as possible, which (ideally) looks… Read More
Applying EDA Concepts Outside Chip Design
(I changed the title of this piece as an experiment) Paul McLellan recently wrote on the topic of new ventures crossing the chasm (getting from initial but bounded success to a proven scalable business). That got me to thinking about the EDA market in general. In some ways it has a similar problem, stuck at $5B or so and single-digit… Read More
S2C ships UltraScale empowering SoFPGA
Most of the discussion around Xilinx UltraScale parts in FPGA-based prototyping modules has been on capacity, and that is certainly a key part of the story. Another use case is developing, one that may be even more important than simply packing a bigger design into a single part without partitioning. The real win with this technology… Read More
Processors Rule the Day
It used to be that if you went to a processor conference, you could expect to spend hours listening to talks about pipelining, cache schemes and processor architecture. Well, I went to the Linley Processor Conference this week in Santa Clara and found the topics pretty compelling. Processors are in just about everything. It is easier… Read More
Five Areas at #53DAC That Require Your Contribution
The 53rd DAC (Design Automation Conference) is some 8 months away, however to make this conference and exhibit another success requires planning, people and awareness. That’s where you come in, because you can contribute your expertise in five different areas:
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IMEC and Cadence Disclose 5nm Test Chip
Recently imec and Cadence disclosed that they had fabricated 5nm test chips. This afternoon Dan Nenni and I had a conference call with Praveen Raghavan, principal engineer at imec, and Vassilios Gerousis, distinguished engineer at Cadence to get more details on what the test chip is and what was learned.
First off Vassilios really… Read More
BATTERYGATE: Is Apple’s Samsung made iPhone 6S Core Rotten?
By this time, anyone with a pulse in the tech industry knows that Apple has dual sourced the A9 processor for the Iphone 6S, from both Samsung and TSMC. There are even apps to tell whether your 6S has a Samsung or TSMC part in it. People have run performance comparisons and concluded that the processing performance is the same, which … Read More
Cadence Outlines Automotive Solutions at TSMC OIP Event
I used to joke that my first car could survive a nuclear war. It was a 1971 Volvo sedan (142) that was EMP proof because it had absolutely no semiconductors in the ignition system, just points, condensers and a coil. If you go back to the Model T in 1915 you will see that the “on-board electronics” were not that different. However, today’s… Read More
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