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Have you ever had a great idea for a new product but then stopped short of following through on it because of the complexities involved to implement it? It’s frustrating to say the least. It is especially frustrating, when the crux of your idea is simple, but complexity arises from required components that don’t add to the functionality… Read More
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There are 3 common misconceptions about debugging FPGA with the real hardware:
[LIST=1]
I was at the 7[SUP]th[/SUP] RISC-V Workshop for two days this week. It was hosted by Western Digital at their headquarters in Milpitas. If you have not been following RISC-V, it is an open source Instruction Set Architecture (ISA) for processor design. The initiative started at Berkeley, and has been catching on like wildfire. … Read More
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When I first started doing IC design back in 1978 we had hierarchical designs, and that was doing a relatively simple 16Kb DRAM chip with only 32,000 transistors using 6um (aka 6,000 nm) design rules. SoC designs today make massive use of hierarchy at all levels of IC design: IC Layout, transistor netlist, gate level netlist, RTL … Read More
Back in the day we had processors which consolidated computing power onto a chip, and out of these sprang (if you’ll excuse the Biblical imagery) microcontrollers (MCUs) in one direction and increasingly complex system-on-chip (SoC) processors in another direction. SoCs are used everywhere today, in smartphones, many IoT … Read More
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TSMC Process Simplification for Advanced Nodes