IEDM Opens with a Big Picture Keynote from TSMC’s Yuh-Jier MiiThe main program for the 70th IEDM opened…Read More
How I learned Formal VerificationBing Xue is a dedicated Formal Verification Engineer at Axiomise,…Read More
Accellera 2024 End of Year UpdateFrom my viewpoint, standards organizations in semiconductor design…Read More
Modern simulators map logic designs into software to compile for native execution on target hardware. Can this compile step be further optimized? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas.… Read More
Analog IC layout is a demanding endeavor as it entails conforming to complex layout design rules, interpreting design intentions from the schematics and understanding arcane topics like transistor matching, noise tolerance, parasitics and latch up. These skills are often handed down from one generation to the next, one on … Read More
Artificial intelligence (AI) has revolutionized data center infrastructure, requiring a reimagining of computational, memory, and connectivity technologies. Meeting the increasing demand for high performance and efficiency in AI workloads has led to the emergence of innovative solutions, including chiplets, advanced… Read More
If you sell sneakers, 1,000 pair is called a humble beginning. On the other hand, selling 1,000 licenses for specialized analog IP is a home run. Silicon Creations celebrated a home run for a critical piece of analog IP that finds its way into a diverse array of applications. Succeeding in so many markets is noteworthy, and I want … Read More
Cadence recently launched a webinar series on trends and challenges in automotive design. They contribute through IP from their Silicon Solutions Group, a comprehensive spectrum of design tooling and through collaborative development within a wide partner ecosystem. This collaboration aims to support and advance progress… Read More
Dan is joined by Rob Knoth, Solutions Architect in the Strategy and New Ventures group at Cadence. He is a technologist focusing on corporate strategy and the interfaces between domain specific solutions. A key area of expertise is the digital implementation of safety critical and high reliability systems. He has extensive experience… Read More
Sandeep Kumar is the Chief Executive of LTSCT (L&T Semiconductor Technologies Ltd). A seasoned technology executive with over 35 years of experience, Kumar has a proven track record in building and scaling technology businesses globally.
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WSTS reported third-quarter 2024 semiconductor market growth of $166 billion, up 10.7 percent from second-quarter 2024. 3Q 2024 growth was the highest quarter-to-quarter growth since 11.6% in 3Q 2016, eight years ago. 3Q 2024 growth versus a year ago was 23.2%, the highest year-to-year growth since 28.3% in 4Q 2021.
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An animated panel discussion Design Automation Conference in June offered up a view of the state of RISC-V and open-source functional verification and a wealth of good material for a three-part blog post series.
Parts One and Two covered a range of topics from microcontroller versus more general-purpose processor versus running… Read More
Next generation semiconductor design puts new stress on traditionally low-key parts of the design process. One example is packaging, which used to be the clean-up spot at the end of the design. Thanks to chiplet-based design, package engineers are now rock stars. Analog design is another one of those disciplines.
Not long ago,… Read More
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