3D ESD verification: Tackling new challenges in advanced IC designBy Dina Medhat Three key takeaways 3D ICs…Read More
Reimagining Architectural Exploration in the Age of AIThis is not about architecting a full SoC…Read More
S2C, MachineWare, and Andes Introduce RISC-V Co-Emulation Solution to Accelerate Chip DevelopmentMachineWare, and Andes Technology today announced a collaborative…Read More
A Webinar About Electrical Verification – The Invisible Bottleneck in IC DesignElectrical rule checking (ERC) is a standard part…Read More
After two years of wrestling with and at least partially resolving fraud charges over its “defeat device” to manipulate emissions testing results, Volkswagen emerged in 2018 as the flag-bearer for electrification in the U.S. The company also concluded 2018 as the largest producer of passenger cars in the world.
In spite of or … Read More
CMP (Chemical Mechanical Planarization or also known as Chemical Mechanical Polishing) is a wafer fabrication step applied generally after a chemical deposition –intended to smoothen and to flatten (planarize) wafer surfaces with the combination of chemical and mechanical forces. Developed at IBM and since its introduction… Read More
At IEDM this December Imec presented “Interconnect metals beyond copper – reliability challenges and opportunities”. In addition to seeing the paper presented I had a chance to interview one of the authors, Kristof Croes. Replacements for copper are a hot subject and I will summarize the challenges and Imec’s work.… Read More
These were the closing words Yunsup Lee, CTO, SiFive used at one of the December RISC-V Summit Keynotes entitled ‘Opportunities and Challenges of Building Silicon in the Cloud’. Fired up was more the mood among the 1000+ attendees of the RISC-V Summit held at the Santa Clara Convention Center and SiFive was among the companies showcasing… Read More
If a picture worths a thousand words, a tapeout quality SoC design with billions of polygons would compose a good book. To proofread this final design transformation format requires a foundry driven DRC/LVS signoff solution that nowadays is becoming more complex with further process scaling and shrinking pitch dimension.
Despite… Read More
Up until 2016, provisioning Ethernet networks was a little bit like buying hot dogs and hot dog buns, in that you could not always match up the quantities to get the most efficient configuration. That dramatically changed when the specification for Ethernet FlexE was adopted by the Optical Internetworking Forum as OIF-FLEXE-01.0.… Read More
Growth in the global economy is expected to slow in 2019 from 2018. Ten economic forecasts released in the last two months show the percentage point change in World GDP from 2018 to 2019 ranging from minus 0.1 points to minus 0.4 points.
[table] border=”1″ cellspacing=”0″ cellpadding=”0″… Read More
One of the more entertaining things I get to observe in the semiconductor ecosystem is competitive customer evaluations of tools and IP. Seriously, this is where the rubber meets the road no matter what the press releases say.
This time it was emulators which is one of the most interesting EDA market segments since there is no dominant… Read More
For those who have been paying any attention to the semiconductor industry its no surprise that memory demand and therefore pricing is down from its peak earlier in the year. Its not getting better any time fast.
After several strong years of demand and pricing, which was followed by enormous CAPEX spending we are seeing the standard… Read More
Nobody likes drama. Wait, let me narrow that down a bit. Chip designers really hate drama. They live in a world of risk and uncertainty, a world that tool and IP vendors spend considerable resources trying to make safer and more rational. It’s notable just how ironic that Sidense and Kilopass were duking out patent litigation in the… Read More
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Quantum Computing Technologies and Challenges