FPGA Prototyping in Practice: Addressing Peripheral Connectivity ChallengesModern chip design verification often encounters challenges when…Read More
An Insight into Building Quantum ComputersGiven my physics background I’m ashamed to admit…Read More
I Have Seen the Future with ChipAgents Autonomous Root Cause AnalysisI have seen a lot of EDA tool…Read More
Arm FCSA and the Journey to Standardizing Open Chiplet-Based DesignI have written before about an inter-chiplet communication…Read More
5G smartphones will increase from just 13 million units in 2019 to 900 million in 2024, as previous 2G/3G/4G smartphones shipments will decline slightly over the 2019-2024 period, reaching parity with 5G smartphones in 3Q 2023, as shown in the chart below.
According to The Information Network’s report “Hot ICs: … Read More
A senior executive from Volkswagen North America kicked off Enterprise Ireland’s first annual “CASE: Driving the Future” mobility symposium last week with the announcement of the launch of its next generation Car-Net connected car platform. The new solution represents a breakthrough by allowing for the customer selection
The 3 way relationship is more complex than it seems
On the surface it seems simple. AMD and TSMC compete with Intel making its own chips and TSMC making them for AMD. But… Read More
Samsung is a complicated company with a VERY long history. We attempted to capture the Samsung Experience in chapter 8 of our book “Mobile Unleashed: The Origin and Evolution of ARM Processors In Our Devices”. If you are a registered SemiWiki member you can download a free PDF copy in our Books section.
Here is the chapter 8 … Read More
Back in May I wrote an article on the new Speedster7t from Achronix. This chip brings together Network on Chip (NoC) interconnect, high speed Ethernet and memory connections, and processing elements optimized for AI/ML. Speedster7t is a very exciting new FPGA that can be used effectively to accelerate a wide range of processing… Read More
Last week I attended the Linley Fall Processor Conference held in Santa Clara, CA. This blog is the first of three blogs I will be writing based on things I saw and heard at the event.
In April, Flex Logix announced its InferX X1 edge inference co-processor. At that time, Flex Logix announced that the IP would be available and that a chip,… Read More
At TechCon Arm announced two more advances against competitive threats, one arguably tactical and the other strategic, at least in this writer’s view. The tactical move was to add support for custom instructions, the ability to collapse multiple instructions into a single instruction through customer-added logic which hooks… Read More
Connecting the Divide between Design and Manufacturing is an overarching theme within the ESD Alliance as these two essential semiconductor disciples become more reliant on each other. It’s also the reason we’re hosting SMART Design, the first system-centric series showcasing advances in electronic system design to be held… Read More
This morning, Synopsys announced its new Die-to-Die PHY IP. This announcement is critically important as it addresses two major market drivers – the growing need for faster connectivity in the datacenter and similar markets, and a path to better exploit the latest processes by dealing with yield issues for larger dies in a different… Read More
The transition to the digital age from a mostly analog world really began with the invention of the A-to-D and D-to-A converters. However scalar processors can easily be overwhelmed by the copious data produced by something as simple as an audio stream. To solve this problem and to really jumpstart the digital age, the development… Read More
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