Revolution EDA: A New EDA Mindset for a New EraMurat Eskiyerli, PhD, is the founder of Revolution…Read More
WEBINAR: Revolutionizing Electrical Verification in IC DesignIn the complex world of IC design, electrical…Read More
Silicon Catalyst on the Road to $1 Trillion IndustryThere were quite a few announcements at the…Read More
Hierarchically defining bump and pin regions overcomes 3D IC complexityBy Todd Burkholder and Per Viklund, Siemens EDA…Read More
As I have mentioned before SemiWiki gets to meet some very smart people and here is another one. Scot Morrison has an MS degree in Aerospace Engineering from MIT specializing in control systems. Today he is the general manager of the Embedded Platform Solutions Division at Mentor, a Siemens business. Scot oversees the Linux®, Nucleus®,… Read More
Is TSMC the real target, not just collateral damage?
Is equipment embargo threat to bring TSMC to heel?
Is an embargo a “Trifecta” of US strategic goals?
Maybe TSMC is a real target of chip equipment embargo not just potential collateral damage
It occurs to us when we talk about TSMC being caught in the middle between … Read More
Economic damage-
China relationship damage will far outlast direct Covid19 logistics impact-
Economic damage could be huge but trade damage could be larger with more specific impact on chips-
A long build up to a China trade nuclear winter, the “drum-beat of war”
When we started talking about a potential chip trade… Read More
TSMC as Pure Play Wafer Foundry
TSMC started its wafer foundry business more than 30 years ago. Visionary management and creative engineering teams developed leading-edge process technologies and their reputation as trusted source for high-volume production. TSMC also recognized very early the importance of building an … Read More
In a previous article [1], the Rayleigh criterion was mentioned as the resolution limit for the distance between two features. On the other hand, in a following article [2], the minimum pitch was mentioned for the resolution limit for arrayed features. In this article, we reconcile the two by considering gaps between arrayed features,… Read More
I’ve spent many years in the ASIC business, and I’ve seen my share of complex chip tapeouts. All of these projects share one important challenge – compute requirements explode when you get close to the finish line. Certain tools need to run on the full-chip layout for final verification and the run times for those tools can get excessively… Read More
Years before ISO 26262 (the auto safety standard) existed, a few electronics engineers had to worry about radiation hardening, but not for cars. Their concerns were the same we have today – radiation-induced single event effects (SEE) and single event upsets (SEU). SEEs are root-cause effects – some form of radiation, might be… Read More
Recently Seeking Alpha published an article “Taiwan Semiconductor Manufacturing Company Losing Its Process Leadership To Intel” and Dan Nenni (SemiWiki founder) asked me to take a look at the article and do my own analysis. This is a subject I have followed and published on for many years.
Before I dig into specific process density… Read More
Anyone who has started a company knows that landing the seed round of investment is just the beginning. There are many decisions to face. When to start building a sales team? What parts of the company’s infrastructure to outsource? How to price and promote your product? These are just a few of the questions to be answered. If your… Read More
During the COVID-19 pandemic I’m using Zoom and attending more webinars to keep updated on semiconductor industry trends, and one huge trend is the importance of AI applied to SoCs. Using more cores to handle ML and DL makes sense, but then how do you keep the chips within their power and reliability limits while at the same … Read More
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