The commonly advanced reason for IP reuse is lower cost and shorter development time. However, IP reuse presents its own challenges, especially for analog designs. In the case of digital designs, once a new standard cell library is available, it is usually not too hard to resynthesize RTL to create new working silicon. For analog… Read More



Innovation in Verification March 2020
This blog is the next in a series in which Paul Cunningham (GM of the Verification Group at Cadence), Jim Hogan and I pick a paper on a novel idea we appreciated and suggest opportunities to further build on that idea.
We welcome comments on our blogs and suggestions for new topics if they’re based on published work.
The Innovation
Our… Read More
5G SoCs Demand New Verification Approaches
Lately, I’ve been cataloging the number of impossible-to-verify technologies we face. All forms of machine learning and inference applications fall into this category. I’ve yet to see a regression test to prove a chip for an autonomous driving system will do the right thing in all cases. Training data bias is another interesting… Read More
Will the Q1 Haircut become Covid-19 Crew Cut in Q2?
- Corona impact growing exponentially in chip food chain
- YMTC in Wuhan may be “patient zero”
- Q1 revenue haircuts may turn into Q2 crewcuts
- Working from home really doesn’t work
When does a haircut become a crew cut in revenues?
All the major semiconductor equipment makers took a significant haircut to their Q1… Read More
The Need for Low Pupil Fill in EUV Lithography
Extreme ultraviolet (EUV) lithography targets sub-20 nm resolution using a wavelength range of ~13.3-13.7 nm (with some light including DUV outside this band as well) and a reflective ring-field optics system. ASML has been refining the EUV tool platform, starting with the NXE:3300B, the very first platform with a numerical
There is No Easy Fix to AI Privacy Problems
Artificial intelligence – more specifically, the machine learning (ML) subset of AI – has a number of privacy problems.
Not only does ML require vast amounts of data for the training process, but the derived system is also provided with access to even greater volumes of data as part of the inference processing while in operation. … Read More
SPIE 2020 – Applied Materials Material-Enabled Patterning
I wasn’t able to attend the SPIE Advanced Lithography Conference this year for personal reasons, but Applied Materials was kind enough to set up a phone briefing for me with Regina Freed to discuss their Materials-Enabled Patterning announcement.
At IEDM Applied Materials (AMAT) tried to put together a panel across the entire… Read More
Why IP Designers Don’t Like Surprises!
If it’s your job to get a SoC design through synthesis, timing/power closure and final verification, the last thing you need are surprises in new versions of the IP blocks that are integrated into the design. If your IP supplier sends a new version, the best possible scenario is that this is only a small incremental change from… Read More
The Story of Ultra-WideBand – Part 4: Short latency is king
How Ultra-wideband aligns with 5G’s premise
In part 3, we discussed the time-frequency duality or how time and bandwidth are interchangeable. If one wants to compress in time a wireless transmission, more frequency bandwidth is needed. This property can be used to increase the accuracy of ranging, as we saw in part 3. Another very… Read More
Turbo-Charge Your Next PCIe SoC with PLDA Switch IP
SemiWiki has a new IP partner, PLDA and they bring a lot to the party. Peripheral component interconnect express (PCIe) is a popular high-performance data interface standard. Think GPUs, RAID cards, WiFi cards or solid-state disk (SSD) drives connected to a motherboard. The protocol offers much higher throughput than previous… Read More
Intel’s Pearl Harbor Moment