Something New in Analog Test AutomationDigital design engineers have used DFT automation technologies…Read More
MediaTek Develops Chip Utilizing TSMC’s 2nm Process, Achieving Milestones in Performance and Power EfficiencyMediaTek’s first chipset using 2nm technology expected in…Read More
Advancing Semiconductor Design: Intel's Foveros 2.5D Packaging TechnologyIn the rapidly evolving landscape of semiconductor manufacturing,…Read More
Synopsys Announces Expanding AI Capabilities and EDA AI LeadershipIn the fast-paced semiconductor industry Synopsys has redefined…Read More
Webinar Preview – Addressing Functional ECOs for Mixed-Signal ASICsAn engineering change order, or ECO in the…Read More
Embedded FPGA use is on the rise. The programmability offered by this kind of IP finds many applications in complex SoCs. There was a recent announcement that OpenFive had licensed Flex Logix’s eFPGA to develop a low power communications SoC. The part required a large eFPGA. The news was reported on SemiWiki here. This announcement… Read More
As regular readers may know, every few months I check in with Cristian Amitroaie, CEO of AMIQ EDA, to see what’s new with the company and their products. In our posts so far this year we’ve focused on verification, and now I’m wondering how an integrated development environment (IDE) provides benefits to designers. They work on huge… Read More
The introduction of direct die-to-die bonding technology into high volume production has the potential to substantially affect the evolution of the microelectronics industry. The concerns relative to the “end of Moore’s Law”, the diminishing returns of continued (monolithic) CMOS process scaling, and the disruptive effect… Read More
US BIS confirms our prediction of “blacklisting” SMIC
SMIC embargoed from 10NM or better technology
Likely related to ASML pressure & WH scorched earth
We had received a lot of feedback on our Nov 30th note regarding blacklisting of SMIC suggesting that we were wrong and the only thing blacklisted… Read More
The Cadence Virtuoso Design System has been one of the premier Integrated Circuit design systems for many years and is used by most major semiconductor companies. While it is powerful and versatile, it is often not optimized for certain complex, repetitive and time-consuming layout design tasks.
The founder and president … Read More
A few weeks ago I wrote about an upcoming event Silicon Catalyst was hosting, the Semiconductor Industry Forum – A View to the Future. I mentioned a high-profile group of presenters: Don Clark, Contributing Journalist, New York Times as moderator; Mark Edelstone, Chairman of Global Semiconductor Investment Banking, Morgan… Read More
Ten years ago, earbuds might have seemed like a mundane product area with little room for exciting developments. Truly Wireless Stereo (TWS) has coincided with an avalanche of innovations that have moved earbuds from a simple transducer for creating sound into being a sophisticated device capable of accepting user commands … Read More
Compute Express Link (CXL), a new open interconnect standard, targets intensive workloads for CPUs and purpose-built accelerators where efficient, coherent memory access between a host and device is required. A consortium to enable this new standard is in place, and a lot of heavy hitters are behind the standard, including … Read More
Normally I would post this Accellera update during DVCon US but, no surprise, this year is weird. Particularly in conferences going virtual. The last DVCon was in early March of this year, right on the cusp of the shutdown. I was there in person, as was Lu Dai (Chairman of Accellera). Both Synopsys and Cadence had dropped out, citing… Read More
The vast majority of the attention given to the introduction of each new advanced process node focuses on lithographic updates. The common metrics quoted are the transistors per mm**2 or the (high-density) SRAM bit cell area. Alternatively, detailed decomposition analysis may be applied using transmission electron microscopy… Read More
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