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IPnest Forecast Interface IP Category Growth to $2.5B in 2025

IPnest Forecast Interface IP Category Growth to $2.5B in 2025
by Eric Esteve on 07-05-2021 at 10:00 am

Interface IP 2016 2025 min

Why should the interface IP category see such a high growth rate until 2025? IP vendors revenues totaled $1068 million in 2020, compared with $872 in 2019. That is 22.4% YoY growth rate and confirm that last year YoY value of 18% was the sign for a long-term growth, as IPnest shows in “Interface IP Survey 2016-2020 & Forecast 2021-2025”,… Read More


On Standards and Open-Sourcing. Verification Talks

On Standards and Open-Sourcing. Verification Talks
by Moshe Zalcberg on 07-05-2021 at 6:00 am

Meetup panel min 1

At Veriest we host VERIFICATION MEETUPS periodically to share verification wisdom. In our virtual meetings we’ve had hundreds of attendants from the US, Europe, Israel, India, and China. Most recently we were able to host a live event in Israel – I want to share feedback from that meeting.

We started with two presentations:… Read More


The Quest for Bugs: “Correct by Design!”

The Quest for Bugs: “Correct by Design!”
by Bryan Dickman on 07-04-2021 at 6:00 am

Title Image

In this article we take an objective view of Virtual Prototyping from the engineering lens and the “quest to find bugs”. In this instance we discuss the avoidance of bugs in terms of architecting complex ASICs to be “correct by design”.

AI Challenges

It is not surprising to find out that other areas of human endeavour, beyond semiconductor… Read More


Podcast EP27: Veriest and its role in the semiconductor ecosystem

Podcast EP27: Veriest and its role in the semiconductor ecosystem
by Daniel Nenni on 07-02-2021 at 10:00 am
Dan and Mike are joined by Moshe Zalcberg, CEO of Veriest. Moshe discusses the changing landscape of semiconductor design and the critical enabling role of companies like Veriest. He reviews the complexity increases that we’ve all seen and suggests ways that Veriest can enable the new and pervasive use of semiconductors
Read More

VLSI Symposium – TSMC and Imec on Advanced Process and Devices Technology Toward 2nm

VLSI Symposium – TSMC and Imec on Advanced Process and Devices Technology Toward 2nm
by Scotten Jones on 07-02-2021 at 6:00 am

Figure 1

At the 2021 Symposium on VLSI Technology and Circuits in June a short course was held on “Advanced Process and Devices Technology Toward 2nm-CMOS and Emerging Memory”. In this article I will review the first two presentations covering leading edge logic devices. The two presentations are complementary and provide and excellent… Read More


Resist Development for High-NA EUV

Resist Development for High-NA EUV
by Tom Dillinger on 07-01-2021 at 10:00 am

EUV scaling

The successful transition to a new fabrication process from development to high volume manufacturing requires a collective, collaborative effort among process engineers, equipment manufacturers, and especially, chemical suppliers.  Of particular importance is the chemistry of the photoresist materials and their interaction… Read More


Achieving Scalability Means No More Silos

Achieving Scalability Means No More Silos
by Mike Gianfagna on 07-01-2021 at 6:00 am

Achieving Scalability Means No More Silos

This is a story of contrasts and counter-intuitive results. Perforce recently published a white paper discussing enterprise scalability – what it takes, why it’s important and what can get in the way. The discussion will shake up some long-held notions regarding effective project management. The results can be significant,… Read More


Safety + Security for Automotive SoCs with ASIL B Compliant tRoot HSMs

Safety + Security for Automotive SoCs with ASIL B Compliant tRoot HSMs
by Kalar Rajendiran on 06-30-2021 at 10:00 am

New Architectures Reshaping Auto SoCs

Automotive segment is a market that has historically been supported by a few select suppliers within the semiconductor ecosystem. Over the last decade, this market has transitioned from just being about reliability, performance, fuel efficiency, etc., to placing equal importance to user experience. This user experience … Read More


What’s New with UVM and UVM Checking?

What’s New with UVM and UVM Checking?
by Daniel Nenni on 06-30-2021 at 6:00 am

UVM and UVM Checking

About once a quarter, I touch base with Cristian Amitroaie, CEO and co-founder of AMIQ EDA, to see what’s new with the company, products, and users. Sometimes he surprises me, as he did earlier this year when he mentioned that their tools check about 150 rules for non-standard constructs in SystemVerilog and VHDL. When we talked … Read More


Neural Nets and CR Testing. Innovation in Verification

Neural Nets and CR Testing. Innovation in Verification
by Bernard Murphy on 06-29-2021 at 10:00 am

Instrumenting Post-Silicon Validation

Leveraging neural nets and CR testing isn’t as simple as we first thought. But is that the last word in combining these two techniques? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO) and I continue our series on research ideas. As always, feedback welcome.… Read More